1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device Tree Bindings for the Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
18 const: arasan,sdhci-5.1
44 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
45 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
46 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
48 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
49 - const: arasan,sdhci-5.1
51 For this device it is strongly suggested to include
52 arasan,soc-ctl-syscon.
54 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
55 - const: arasan,sdhci-8.9a
57 For this device it is strongly suggested to include
58 clock-output-names and '#clock-cells'.
60 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
61 - const: arasan,sdhci-8.9a
63 For this device it is strongly suggested to include
64 clock-output-names and '#clock-cells'.
66 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
67 - const: arasan,sdhci-5.1
69 For this device it is strongly suggested to include
70 arasan,soc-ctl-syscon.
72 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
73 - const: arasan,sdhci-5.1
75 For this device it is strongly suggested to include
76 arasan,soc-ctl-syscon.
78 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79 - const: arasan,sdhci-5.1
81 For this device it is strongly suggested to include
82 arasan,soc-ctl-syscon.
83 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
85 For this device it is strongly suggested to include
86 arasan,soc-ctl-syscon.
87 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
89 For this device it is strongly suggested to include
90 arasan,soc-ctl-syscon.
92 - const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
93 - const: arasan,sdhci-5.1
95 For this device it is strongly suggested to include
96 clock-output-names and '#clock-cells'.
124 arasan,soc-ctl-syscon:
125 $ref: /schemas/types.yaml#/definitions/phandle
127 A phandle to a syscon device (see ../mfd/syscon.txt) used to access
128 core corecfg registers. Offsets of registers in this syscon are
129 determined based on the main compatible string for the device.
135 Name of the card clock which will be exposed by this device.
140 With this property in place we will export one or two clocks
141 representing the Card Clock. These clocks are expected to be
144 xlnx,fails-without-test-cd:
145 $ref: /schemas/types.yaml#/definitions/flag
147 When present, the controller doesn't work when the CD line is not
148 connected properly, and the line is not connected properly.
149 Test mode can be used to force the controller to function.
151 xlnx,int-clock-stable-broken:
152 $ref: /schemas/types.yaml#/definitions/flag
154 When present, the controller always reports that the internal clock
155 is stable even when it is not.
158 $ref: /schemas/types.yaml#/definitions/uint32
162 The MIO bank number in which the command and data lines are configured.
165 '#clock-cells': [ clock-output-names ]
174 unevaluatedProperties: false
179 compatible = "arasan,sdhci-8.9a";
180 reg = <0xe0100000 0x1000>;
181 clock-names = "clk_xin", "clk_ahb";
182 clocks = <&clkc 21>, <&clkc 32>;
183 interrupt-parent = <&gic>;
184 interrupts = <0 24 4>;
189 compatible = "arasan,sdhci-5.1";
190 reg = <0xe2800000 0x1000>;
191 clock-names = "clk_xin", "clk_ahb";
192 clocks = <&cru 8>, <&cru 18>;
193 interrupt-parent = <&gic>;
194 interrupts = <0 24 4>;
196 phy-names = "phy_arasan";
200 #include <dt-bindings/clock/rk3399-cru.h>
201 #include <dt-bindings/interrupt-controller/arm-gic.h>
202 #include <dt-bindings/interrupt-controller/irq.h>
204 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
205 reg = <0xfe330000 0x10000>;
206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
208 clock-names = "clk_xin", "clk_ahb";
209 arasan,soc-ctl-syscon = <&grf>;
210 assigned-clocks = <&cru SCLK_EMMC>;
211 assigned-clock-rates = <200000000>;
212 clock-output-names = "emmc_cardclock";
214 phy-names = "phy_arasan";
220 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
221 interrupt-parent = <&gic>;
222 interrupts = <0 48 4>;
223 reg = <0xff160000 0x1000>;
224 clocks = <&clk200>, <&clk200>;
225 clock-names = "clk_xin", "clk_ahb";
226 clock-output-names = "clk_out_sd0", "clk_in_sd0";
228 clk-phase-sd-hs = <63>, <72>;
233 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
234 interrupt-parent = <&gic>;
235 interrupts = <0 126 4>;
236 reg = <0xf1040000 0x10000>;
237 clocks = <&clk200>, <&clk200>;
238 clock-names = "clk_xin", "clk_ahb";
239 clock-output-names = "clk_out_sd0", "clk_in_sd0";
241 clk-phase-sd-hs = <132>, <60>;
245 #define LGM_CLK_EMMC5
247 #define LGM_GCLK_EMMC
249 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
250 reg = <0xec700000 0x300>;
251 interrupt-parent = <&ioapic1>;
253 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
254 <&cgu0 LGM_GCLK_EMMC>;
255 clock-names = "clk_xin", "clk_ahb", "gate";
256 clock-output-names = "emmc_cardclock";
259 phy-names = "phy_arasan";
260 arasan,soc-ctl-syscon = <&sysconf>;
265 #define LGM_GCLK_SDXC
267 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
268 reg = <0xec600000 0x300>;
269 interrupt-parent = <&ioapic1>;
271 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
272 <&cgu0 LGM_GCLK_SDXC>;
273 clock-names = "clk_xin", "clk_ahb", "gate";
274 clock-output-names = "sdxc_cardclock";
277 phy-names = "phy_arasan";
278 arasan,soc-ctl-syscon = <&sysconf>;
282 #define KEEM_BAY_PSS_AUX_EMMC
283 #define KEEM_BAY_PSS_EMMC
285 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
286 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
287 reg = <0x33000000 0x300>;
288 clock-names = "clk_xin", "clk_ahb";
289 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
290 <&scmi_clk KEEM_BAY_PSS_EMMC>;
292 phy-names = "phy_arasan";
293 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
294 assigned-clock-rates = <200000000>;
295 clock-output-names = "emmc_cardclock";
297 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
301 #define KEEM_BAY_PSS_AUX_SD0
302 #define KEEM_BAY_PSS_SD0
304 compatible = "intel,keembay-sdhci-5.1-sd";
305 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
306 reg = <0x31000000 0x300>;
307 clock-names = "clk_xin", "clk_ahb";
308 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
309 <&scmi_clk KEEM_BAY_PSS_SD0>;
310 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
316 #define TBH_PSS_EMMC_RST_N
318 compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
319 interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
320 reg = <0x80420000 0x400>;
321 clocks = <&scmi_clk EMMC_XIN_CLK>,
322 <&scmi_clk EMMC_AXI_CLK>;
323 clock-names = "clk_xin", "clk_ahb";
325 phy-names = "phy_arasan";
326 assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
327 clock-output-names = "emmc_cardclock";
328 resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
329 #clock-cells = <0x0>;