1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device Tree Bindings for the Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
18 const: arasan,sdhci-5.1
44 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
45 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
46 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
48 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
49 - const: arasan,sdhci-5.1
51 For this device it is strongly suggested to include
52 arasan,soc-ctl-syscon.
54 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
55 - const: arasan,sdhci-8.9a
57 For this device it is strongly suggested to include
58 clock-output-names and '#clock-cells'.
60 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
61 - const: arasan,sdhci-8.9a
63 For this device it is strongly suggested to include
64 clock-output-names and '#clock-cells'.
66 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
67 - const: arasan,sdhci-5.1
69 For this device it is strongly suggested to include
70 arasan,soc-ctl-syscon.
72 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
73 - const: arasan,sdhci-5.1
75 For this device it is strongly suggested to include
76 arasan,soc-ctl-syscon.
78 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79 - const: arasan,sdhci-5.1
81 For this device it is strongly suggested to include
82 arasan,soc-ctl-syscon.
83 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
85 For this device it is strongly suggested to include
86 arasan,soc-ctl-syscon.
87 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
89 For this device it is strongly suggested to include
90 arasan,soc-ctl-syscon.
115 arasan,soc-ctl-syscon:
116 $ref: /schemas/types.yaml#/definitions/phandle
118 A phandle to a syscon device (see ../mfd/syscon.txt) used to access
119 core corecfg registers. Offsets of registers in this syscon are
120 determined based on the main compatible string for the device.
126 Name of the card clock which will be exposed by this device.
131 With this property in place we will export one or two clocks
132 representing the Card Clock. These clocks are expected to be
135 xlnx,fails-without-test-cd:
136 $ref: /schemas/types.yaml#/definitions/flag
138 When present, the controller doesn't work when the CD line is not
139 connected properly, and the line is not connected properly.
140 Test mode can be used to force the controller to function.
142 xlnx,int-clock-stable-broken:
143 $ref: /schemas/types.yaml#/definitions/flag
145 When present, the controller always reports that the internal clock
146 is stable even when it is not.
149 $ref: /schemas/types.yaml#/definitions/uint32
153 The MIO bank number in which the command and data lines are configured.
156 clock-output-names: [ '#clock-cells' ]
157 '#clock-cells': [ clock-output-names ]
166 unevaluatedProperties: false
171 compatible = "arasan,sdhci-8.9a";
172 reg = <0xe0100000 0x1000>;
173 clock-names = "clk_xin", "clk_ahb";
174 clocks = <&clkc 21>, <&clkc 32>;
175 interrupt-parent = <&gic>;
176 interrupts = <0 24 4>;
181 compatible = "arasan,sdhci-5.1";
182 reg = <0xe2800000 0x1000>;
183 clock-names = "clk_xin", "clk_ahb";
184 clocks = <&cru 8>, <&cru 18>;
185 interrupt-parent = <&gic>;
186 interrupts = <0 24 4>;
188 phy-names = "phy_arasan";
192 #include <dt-bindings/clock/rk3399-cru.h>
193 #include <dt-bindings/interrupt-controller/arm-gic.h>
194 #include <dt-bindings/interrupt-controller/irq.h>
196 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
197 reg = <0xfe330000 0x10000>;
198 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
200 clock-names = "clk_xin", "clk_ahb";
201 arasan,soc-ctl-syscon = <&grf>;
202 assigned-clocks = <&cru SCLK_EMMC>;
203 assigned-clock-rates = <200000000>;
204 clock-output-names = "emmc_cardclock";
206 phy-names = "phy_arasan";
212 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
213 interrupt-parent = <&gic>;
214 interrupts = <0 48 4>;
215 reg = <0xff160000 0x1000>;
216 clocks = <&clk200>, <&clk200>;
217 clock-names = "clk_xin", "clk_ahb";
218 clock-output-names = "clk_out_sd0", "clk_in_sd0";
220 clk-phase-sd-hs = <63>, <72>;
225 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
226 interrupt-parent = <&gic>;
227 interrupts = <0 126 4>;
228 reg = <0xf1040000 0x10000>;
229 clocks = <&clk200>, <&clk200>;
230 clock-names = "clk_xin", "clk_ahb";
231 clock-output-names = "clk_out_sd0", "clk_in_sd0";
233 clk-phase-sd-hs = <132>, <60>;
237 #define LGM_CLK_EMMC5
239 #define LGM_GCLK_EMMC
241 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
242 reg = <0xec700000 0x300>;
243 interrupt-parent = <&ioapic1>;
245 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
246 <&cgu0 LGM_GCLK_EMMC>;
247 clock-names = "clk_xin", "clk_ahb", "gate";
248 clock-output-names = "emmc_cardclock";
251 phy-names = "phy_arasan";
252 arasan,soc-ctl-syscon = <&sysconf>;
257 #define LGM_GCLK_SDXC
259 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
260 reg = <0xec600000 0x300>;
261 interrupt-parent = <&ioapic1>;
263 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
264 <&cgu0 LGM_GCLK_SDXC>;
265 clock-names = "clk_xin", "clk_ahb", "gate";
266 clock-output-names = "sdxc_cardclock";
269 phy-names = "phy_arasan";
270 arasan,soc-ctl-syscon = <&sysconf>;
274 #define KEEM_BAY_PSS_AUX_EMMC
275 #define KEEM_BAY_PSS_EMMC
277 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
278 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
279 reg = <0x33000000 0x300>;
280 clock-names = "clk_xin", "clk_ahb";
281 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
282 <&scmi_clk KEEM_BAY_PSS_EMMC>;
284 phy-names = "phy_arasan";
285 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
286 assigned-clock-rates = <200000000>;
287 clock-output-names = "emmc_cardclock";
289 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
293 #define KEEM_BAY_PSS_AUX_SD0
294 #define KEEM_BAY_PSS_SD0
296 compatible = "intel,keembay-sdhci-5.1-sd";
297 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
298 reg = <0x31000000 0x300>;
299 clock-names = "clk_xin", "clk_ahb";
300 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
301 <&scmi_clk KEEM_BAY_PSS_SD0>;
302 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;