Documentation/devicetree/bindings/mips/mscc.txt

   1 * Microsemi MIPS CPUs
   2
   3 Boards with a SoC of the Microsemi MIPS family shall have the following
   4 properties:
   5
   6 Required properties:
   7 - compatible: "mscc,ocelot"
   8
   9
  10 * Other peripherals:
  11
  12 o CPU chip regs:
  13
  14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
  15 functionalities: chip ID, general purpose register for software use, reset
  16 controller, hardware status and configuration, efuses.
  17
  18 Required properties:
  19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
  20 - reg : Should contain registers location and length
  21
  22 Example:
  23         syscon@71070000 {
  24                 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
  25                 reg = <0x71070000 0x1c>;
  26         };
  27
  28
  29 o CPU system control:
  30
  31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
  32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
  33 endianness, CPU bus control, CPU status.
  34
  35 Required properties:
  36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
  37 - reg : Should contain registers location and length
  38
  39 Example:
  40         syscon@70000000 {
  41                 compatible = "mscc,ocelot-cpu-syscon", "syscon";
  42                 reg = <0x70000000 0x2c>;
  43         };