Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml

   1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Ocelot Externally-Controlled Ethernet Switch
   8
   9 maintainers:
  10   - Colin Foster <colin.foster@in-advantage.com>
  11
  12 description: |
  13   The Ocelot ethernet switch family contains chips that have an internal CPU
  14   (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
  15   the option to be controlled externally, which is the purpose of this driver.
  16
  17   The switch family is a multi-port networking switch that supports many
  18   interfaces. Additionally, the device can perform pin control, MDIO buses, and
  19   external GPIO expanders.
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - mscc,vsc7512
  25
  26   reg:
  27     maxItems: 1
  28
  29   "#address-cells":
  30     const: 1
  31
  32   "#size-cells":
  33     const: 1
  34
  35   spi-max-frequency:
  36     maxItems: 1
  37
  38 patternProperties:
  39   "^pinctrl@[0-9a-f]+$":
  40     type: object
  41     $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
  42
  43   "^gpio@[0-9a-f]+$":
  44     type: object
  45     $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
  46     properties:
  47       compatible:
  48         enum:
  49           - mscc,ocelot-sgpio
  50
  51   "^mdio@[0-9a-f]+$":
  52     type: object
  53     $ref: /schemas/net/mscc,miim.yaml
  54     properties:
  55       compatible:
  56         enum:
  57           - mscc,ocelot-miim
  58
  59 required:
  60   - compatible
  61   - reg
  62   - '#address-cells'
  63   - '#size-cells'
  64   - spi-max-frequency
  65
  66 additionalProperties: false
  67
  68 examples:
  69   - |
  70     ocelot_clock: ocelot-clock {
  71           compatible = "fixed-clock";
  72           #clock-cells = <0>;
  73           clock-frequency = <125000000>;
  74       };
  75
  76     spi {
  77         #address-cells = <1>;
  78         #size-cells = <0>;
  79
  80         soc@0 {
  81             compatible = "mscc,vsc7512";
  82             spi-max-frequency = <2500000>;
  83             reg = <0>;
  84             #address-cells = <1>;
  85             #size-cells = <1>;
  86
  87             mdio@7107009c {
  88                 compatible = "mscc,ocelot-miim";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 reg = <0x7107009c 0x24>;
  92
  93                 sw_phy0: ethernet-phy@0 {
  94                     reg = <0x0>;
  95                 };
  96             };
  97
  98             mdio@710700c0 {
  99                 compatible = "mscc,ocelot-miim";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&miim1_pins>;
 102                 #address-cells = <1>;
 103                 #size-cells = <0>;
 104                 reg = <0x710700c0 0x24>;
 105
 106                 sw_phy4: ethernet-phy@4 {
 107                     reg = <0x4>;
 108                 };
 109             };
 110
 111             gpio: pinctrl@71070034 {
 112                 compatible = "mscc,ocelot-pinctrl";
 113                 gpio-controller;
 114                 #gpio-cells = <2>;
 115                 gpio-ranges = <&gpio 0 0 22>;
 116                 reg = <0x71070034 0x6c>;
 117
 118                 sgpio_pins: sgpio-pins {
 119                     pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 120                     function = "sg0";
 121                 };
 122
 123                 miim1_pins: miim1-pins {
 124                     pins = "GPIO_14", "GPIO_15";
 125                     function = "miim";
 126                 };
 127             };
 128
 129             gpio@710700f8 {
 130                 compatible = "mscc,ocelot-sgpio";
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 bus-frequency = <12500000>;
 134                 clocks = <&ocelot_clock>;
 135                 microchip,sgpio-port-ranges = <0 15>;
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&sgpio_pins>;
 138                 reg = <0x710700f8 0x100>;
 139
 140                 sgpio_in0: gpio@0 {
 141                     compatible = "microchip,sparx5-sgpio-bank";
 142                     reg = <0>;
 143                     gpio-controller;
 144                     #gpio-cells = <3>;
 145                     ngpios = <64>;
 146                 };
 147
 148                 sgpio_out1: gpio@1 {
 149                     compatible = "microchip,sparx5-sgpio-bank";
 150                     reg = <1>;
 151                     gpio-controller;
 152                     #gpio-cells = <3>;
 153                     ngpios = <64>;
 154                 };
 155             };
 156         };
 157     };
 158
 159 ...
 160