Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml

   1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Ocelot Externally-Controlled Ethernet Switch
   8
   9 maintainers:
  10   - Colin Foster <colin.foster@in-advantage.com>
  11
  12 description: |
  13   The Ocelot ethernet switch family contains chips that have an internal CPU
  14   (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
  15   the option to be controlled externally via external interfaces like SPI or
  16   PCIe.
  17
  18   The switch family is a multi-port networking switch that supports many
  19   interfaces. Additionally, the device can perform pin control, MDIO buses, and
  20   external GPIO expanders.
  21
  22 properties:
  23   compatible:
  24     enum:
  25       - mscc,vsc7512
  26
  27   reg:
  28     maxItems: 1
  29
  30   "#address-cells":
  31     const: 1
  32
  33   "#size-cells":
  34     const: 1
  35
  36   spi-max-frequency:
  37     maxItems: 1
  38
  39 patternProperties:
  40   "^pinctrl@[0-9a-f]+$":
  41     type: object
  42     $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
  43
  44   "^gpio@[0-9a-f]+$":
  45     type: object
  46     $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
  47     properties:
  48       compatible:
  49         enum:
  50           - mscc,ocelot-sgpio
  51
  52   "^mdio@[0-9a-f]+$":
  53     type: object
  54     $ref: /schemas/net/mscc,miim.yaml
  55     properties:
  56       compatible:
  57         enum:
  58           - mscc,ocelot-miim
  59
  60   "^ethernet-switch@[0-9a-f]+$":
  61     type: object
  62     $ref: /schemas/net/mscc,vsc7514-switch.yaml
  63     unevaluatedProperties: false
  64     properties:
  65       compatible:
  66         enum:
  67           - mscc,vsc7512-switch
  68
  69 required:
  70   - compatible
  71   - reg
  72   - '#address-cells'
  73   - '#size-cells'
  74
  75 additionalProperties: false
  76
  77 examples:
  78   - |
  79     ocelot_clock: ocelot-clock {
  80           compatible = "fixed-clock";
  81           #clock-cells = <0>;
  82           clock-frequency = <125000000>;
  83       };
  84
  85     spi {
  86         #address-cells = <1>;
  87         #size-cells = <0>;
  88
  89         soc@0 {
  90             compatible = "mscc,vsc7512";
  91             spi-max-frequency = <2500000>;
  92             reg = <0>;
  93             #address-cells = <1>;
  94             #size-cells = <1>;
  95
  96             mdio@7107009c {
  97                 compatible = "mscc,ocelot-miim";
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 reg = <0x7107009c 0x24>;
 101
 102                 sw_phy0: ethernet-phy@0 {
 103                     reg = <0x0>;
 104                 };
 105             };
 106
 107             mdio@710700c0 {
 108                 compatible = "mscc,ocelot-miim";
 109                 pinctrl-names = "default";
 110                 pinctrl-0 = <&miim1_pins>;
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 reg = <0x710700c0 0x24>;
 114
 115                 sw_phy4: ethernet-phy@4 {
 116                     reg = <0x4>;
 117                 };
 118             };
 119
 120             gpio: pinctrl@71070034 {
 121                 compatible = "mscc,ocelot-pinctrl";
 122                 gpio-controller;
 123                 #gpio-cells = <2>;
 124                 gpio-ranges = <&gpio 0 0 22>;
 125                 reg = <0x71070034 0x6c>;
 126
 127                 sgpio_pins: sgpio-pins {
 128                     pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 129                     function = "sg0";
 130                 };
 131
 132                 miim1_pins: miim1-pins {
 133                     pins = "GPIO_14", "GPIO_15";
 134                     function = "miim";
 135                 };
 136             };
 137
 138             gpio@710700f8 {
 139                 compatible = "mscc,ocelot-sgpio";
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142                 bus-frequency = <12500000>;
 143                 clocks = <&ocelot_clock>;
 144                 microchip,sgpio-port-ranges = <0 15>;
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&sgpio_pins>;
 147                 reg = <0x710700f8 0x100>;
 148
 149                 sgpio_in0: gpio@0 {
 150                     compatible = "microchip,sparx5-sgpio-bank";
 151                     reg = <0>;
 152                     gpio-controller;
 153                     #gpio-cells = <3>;
 154                     ngpios = <64>;
 155                 };
 156
 157                 sgpio_out1: gpio@1 {
 158                     compatible = "microchip,sparx5-sgpio-bank";
 159                     reg = <1>;
 160                     gpio-controller;
 161                     #gpio-cells = <3>;
 162                     ngpios = <64>;
 163                 };
 164             };
 165         };
 166     };
 167
 168 ...
 169