Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX8qm/qxp Control and Status Registers Module
   8
   9 maintainers:
  10   - Liu Ying <victor.liu@nxp.com>
  11
  12 description: |
  13   As a system controller, the Freescale i.MX8qm/qxp Control and Status
  14   Registers(CSR) module represents a set of miscellaneous registers of a
  15   specific subsystem.  It may provide control and/or status report interfaces
  16   to a mix of standalone hardware devices within that subsystem.  One typical
  17   use-case is for some other nodes to acquire a reference to the syscon node
  18   by phandle, and the other typical use-case is that the operating system
  19   should consider all subnodes of the CSR module as separate child devices.
  20
  21 properties:
  22   $nodename:
  23     pattern: "^syscon@[0-9a-f]+$"
  24
  25   compatible:
  26     items:
  27       - enum:
  28           - fsl,imx8qxp-mipi-lvds-csr
  29           - fsl,imx8qm-lvds-csr
  30       - const: syscon
  31       - const: simple-mfd
  32
  33   reg:
  34     maxItems: 1
  35
  36   clocks:
  37     maxItems: 1
  38
  39   clock-names:
  40     const: ipg
  41
  42 patternProperties:
  43   "^(ldb|phy|pxl2dpi)$":
  44     type: object
  45     description: The possible child devices of the CSR module.
  46
  47 required:
  48   - compatible
  49   - reg
  50   - clocks
  51   - clock-names
  52
  53 allOf:
  54   - if:
  55       properties:
  56         compatible:
  57           contains:
  58             const: fsl,imx8qxp-mipi-lvds-csr
  59     then:
  60       required:
  61         - pxl2dpi
  62         - ldb
  63
  64   - if:
  65       properties:
  66         compatible:
  67           contains:
  68             const: fsl,imx8qm-lvds-csr
  69     then:
  70       required:
  71         - phy
  72         - ldb
  73
  74 additionalProperties: false
  75
  76 examples:
  77   - |
  78     #include <dt-bindings/clock/imx8-lpcg.h>
  79     #include <dt-bindings/firmware/imx/rsrc.h>
  80     mipi_lvds_0_csr: syscon@56221000 {
  81         compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
  82         reg = <0x56221000 0x1000>;
  83         clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
  84         clock-names = "ipg";
  85
  86         mipi_lvds_0_pxl2dpi: pxl2dpi {
  87             compatible = "fsl,imx8qxp-pxl2dpi";
  88             fsl,sc-resource = <IMX_SC_R_MIPI_0>;
  89             power-domains = <&pd IMX_SC_R_MIPI_0>;
  90
  91             ports {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 port@0 {
  96                     #address-cells = <1>;
  97                     #size-cells = <0>;
  98                     reg = <0>;
  99
 100                     mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
 101                         reg = <0>;
 102                         remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
 103                     };
 104
 105                     mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
 106                         reg = <1>;
 107                         remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
 108                     };
 109                 };
 110
 111                 port@1 {
 112                     #address-cells = <1>;
 113                     #size-cells = <0>;
 114                     reg = <1>;
 115
 116                     mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
 117                         reg = <0>;
 118                         remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
 119                     };
 120
 121                     mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
 122                         reg = <1>;
 123                         remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
 124                     };
 125                 };
 126             };
 127         };
 128
 129         mipi_lvds_0_ldb: ldb {
 130             #address-cells = <1>;
 131             #size-cells = <0>;
 132             compatible = "fsl,imx8qxp-ldb";
 133             clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
 134                      <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
 135             clock-names = "pixel", "bypass";
 136             power-domains = <&pd IMX_SC_R_LVDS_0>;
 137
 138             channel@0 {
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 reg = <0>;
 142                 phys = <&mipi_lvds_0_phy>;
 143                 phy-names = "lvds_phy";
 144
 145                 port@0 {
 146                     reg = <0>;
 147
 148                     mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
 149                         remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
 150                     };
 151                 };
 152
 153                 port@1 {
 154                     reg = <1>;
 155
 156                     /* ... */
 157                 };
 158             };
 159
 160             channel@1 {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 reg = <1>;
 164                 phys = <&mipi_lvds_0_phy>;
 165                 phy-names = "lvds_phy";
 166
 167                 port@0 {
 168                     reg = <0>;
 169
 170                     mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
 171                         remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
 172                     };
 173                 };
 174
 175                 port@1 {
 176                     reg = <1>;
 177
 178                     /* ... */
 179                 };
 180             };
 181         };
 182     };
 183
 184     mipi_lvds_0_phy: phy@56228300 {
 185         compatible = "fsl,imx8qxp-mipi-dphy";
 186         reg = <0x56228300 0x100>;
 187         clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
 188         clock-names = "phy_ref";
 189         #phy-cells = <0>;
 190         fsl,syscon = <&mipi_lvds_0_csr>;
 191         power-domains = <&pd IMX_SC_R_MIPI_0>;
 192     };