1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Control and Status Registers Module
10 - Liu Ying <victor.liu@nxp.com>
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
14 Registers(CSR) module represents a set of miscellaneous registers of a
15 specific subsystem. It may provide control and/or status report interfaces
16 to a mix of standalone hardware devices within that subsystem. One typical
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
19 should consider all subnodes of the CSR module as separate child devices.
23 pattern: "^syscon@[0-9a-f]+$"
28 - fsl,imx8qxp-mipi-lvds-csr
43 "^(ldb|phy|pxl2dpi)$":
45 description: The possible child devices of the CSR module.
58 const: fsl,imx8qxp-mipi-lvds-csr
68 const: fsl,imx8qm-lvds-csr
74 additionalProperties: false
78 #include <dt-bindings/clock/imx8-lpcg.h>
79 #include <dt-bindings/firmware/imx/rsrc.h>
80 mipi_lvds_0_csr: syscon@56221000 {
81 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
82 reg = <0x56221000 0x1000>;
83 clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
86 mipi_lvds_0_pxl2dpi: pxl2dpi {
87 compatible = "fsl,imx8qxp-pxl2dpi";
88 fsl,sc-resource = <IMX_SC_R_MIPI_0>;
89 power-domains = <&pd IMX_SC_R_MIPI_0>;
100 mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
102 remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
105 mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
107 remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
112 #address-cells = <1>;
116 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
118 remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
121 mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
123 remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
129 mipi_lvds_0_ldb: ldb {
130 #address-cells = <1>;
132 compatible = "fsl,imx8qxp-ldb";
133 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
134 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
135 clock-names = "pixel", "bypass";
136 power-domains = <&pd IMX_SC_R_LVDS_0>;
139 #address-cells = <1>;
142 phys = <&mipi_lvds_0_phy>;
143 phy-names = "lvds_phy";
148 mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
149 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
161 #address-cells = <1>;
164 phys = <&mipi_lvds_0_phy>;
165 phy-names = "lvds_phy";
170 mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
171 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
184 mipi_lvds_0_phy: phy@56228300 {
185 compatible = "fsl,imx8qxp-mipi-dphy";
186 reg = <0x56228300 0x100>;
187 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
188 clock-names = "phy_ref";
190 fsl,syscon = <&mipi_lvds_0_csr>;
191 power-domains = <&pd IMX_SC_R_MIPI_0>;