1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 PRCM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun6i-a31-prcm
25 unevaluatedProperties: false
30 - allwinner,sun4i-a10-mod0-clk
31 - allwinner,sun6i-a31-apb0-clk
32 - allwinner,sun6i-a31-apb0-gates-clk
33 - allwinner,sun6i-a31-ar100-clk
34 - allwinner,sun6i-a31-clock-reset
42 const: fixed-factor-clock
45 $ref: /schemas/clock/fixed-factor-clock.yaml#
51 const: allwinner,sun4i-a10-mod0-clk
58 # Already checked in the main schema
75 additionalProperties: false
81 const: allwinner,sun6i-a31-apb0-clk
88 # Already checked in the main schema
105 additionalProperties: false
111 const: allwinner,sun6i-a31-apb0-gates-clk
118 This additional argument passed to that clock is the
119 offset of the bit controlling this particular gate in
122 # Already checked in the main schema
140 additionalProperties: false
146 const: allwinner,sun6i-a31-ar100-clk
153 # Already checked in the main schema
159 The parent order must match the hardware programming
173 additionalProperties: false
179 const: allwinner,sun6i-a31-clock-reset
186 # Already checked in the main schema
195 additionalProperties: false
201 additionalProperties: false
205 #include <dt-bindings/clock/sun6i-a31-ccu.h>
208 compatible = "allwinner,sun6i-a31-prcm";
209 reg = <0x01f01400 0x200>;
212 compatible = "allwinner,sun6i-a31-ar100-clk";
214 clocks = <&rtc 0>, <&osc24M>,
215 <&ccu CLK_PLL_PERIPH>,
216 <&ccu CLK_PLL_PERIPH>;
217 clock-output-names = "ar100";
221 compatible = "fixed-factor-clock";
226 clock-output-names = "ahb0";
230 compatible = "allwinner,sun6i-a31-apb0-clk";
233 clock-output-names = "apb0";
236 apb0_gates: apb0_gates_clk {
237 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
240 clock-output-names = "apb0_pio", "apb0_ir",
241 "apb0_timer", "apb0_p2wi",
242 "apb0_uart", "apb0_1wire",
248 compatible = "allwinner,sun4i-a10-mod0-clk";
249 clocks = <&rtc 0>, <&osc24M>;
250 clock-output-names = "ir";
254 compatible = "allwinner,sun6i-a31-clock-reset";