1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 PRCM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun6i-a31-prcm
25 unevaluatedProperties: false
30 - allwinner,sun4i-a10-mod0-clk
31 - allwinner,sun6i-a31-apb0-clk
32 - allwinner,sun6i-a31-apb0-gates-clk
33 - allwinner,sun6i-a31-ar100-clk
34 - allwinner,sun6i-a31-clock-reset
45 const: fixed-factor-clock
48 $ref: /schemas/clock/fixed-factor-clock.yaml#
54 const: allwinner,sun4i-a10-mod0-clk
76 const: allwinner,sun6i-a31-apb0-clk
98 const: allwinner,sun6i-a31-apb0-gates-clk
105 This additional argument passed to that clock is the
106 offset of the bit controlling this particular gate in
125 const: allwinner,sun6i-a31-ar100-clk
135 The parent order must match the hardware programming
150 const: allwinner,sun6i-a31-clock-reset
164 additionalProperties: false
168 #include <dt-bindings/clock/sun6i-a31-ccu.h>
171 compatible = "allwinner,sun6i-a31-prcm";
172 reg = <0x01f01400 0x200>;
175 compatible = "allwinner,sun6i-a31-ar100-clk";
177 clocks = <&rtc 0>, <&osc24M>,
178 <&ccu CLK_PLL_PERIPH>,
179 <&ccu CLK_PLL_PERIPH>;
180 clock-output-names = "ar100";
184 compatible = "fixed-factor-clock";
189 clock-output-names = "ahb0";
193 compatible = "allwinner,sun6i-a31-apb0-clk";
196 clock-output-names = "apb0";
199 apb0_gates: apb0_gates_clk {
200 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
203 clock-output-names = "apb0_pio", "apb0_ir",
204 "apb0_timer", "apb0_p2wi",
205 "apb0_uart", "apb0_1wire",
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 clocks = <&rtc 0>, <&osc24M>;
213 clock-output-names = "ir";
217 compatible = "allwinner,sun6i-a31-clock-reset";