1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
16 which correct single bit ECC errors and detect double bit ECC errors.
20 const: xlnx,versal-ddrmc
24 - description: DDR Memory Controller registers
25 - description: NOC registers corresponding to DDR Memory Controller
41 additionalProperties: false
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 memory-controller@f6150000 {
51 compatible = "xlnx,versal-ddrmc";
52 reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
53 reg-names = "base", "noc";
54 interrupt-parent = <&gic>;
55 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;