1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC Memory Controller
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The GPMC is a unified memory controller dedicated for interfacing
15 with external memory devices like
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
47 Functional clock. Used for bus timing calculations and
59 - description: DMA channel for GPMC NAND prefetch
65 "#address-cells": true
70 description: maximum number of supported chip-select lines.
71 $ref: /schemas/types.yaml#/definitions/uint32
74 description: maximum number of supported wait pins.
75 $ref: /schemas/types.yaml#/definitions/uint32
80 Must be set up to reflect the memory layout with four
81 integer values for each chip-select line in use,
82 <cs-number> 0 <physical address of mapping> <size>
84 - description: NAND bank 0
85 - description: NOR/SRAM bank 0
86 - description: NOR/SRAM bank 1
93 The GPMC driver implements an interrupt controller for
94 the NAND events "fifoevent" and "termcount" plus the
95 rising/falling edges on the GPMC_WAIT pins.
96 The interrupt number mapping is as follows
99 2 - GPMC_WAIT0 pin edge
100 3 - GPMC_WAIT1 pin edge, and so on.
107 The GPMC driver implements a GPIO controller for the
108 GPMC WAIT pins that can be used as general purpose inputs.
109 0 maps to GPMC_WAIT0 pin.
113 Name of the HWMOD associated with GPMC. This is for legacy
114 omap2/3 platforms only.
115 $ref: /schemas/types.yaml#/definitions/string
120 Prevent idling the module at init. This is for legacy omap2/3
129 The child device node represents the device connected to the GPMC
130 bus. The device can be a NAND chip, SRAM device, NOR device
132 $ref: ti,gpmc-child.yaml
133 additionalProperties: true
154 additionalProperties: false
158 #include <dt-bindings/interrupt-controller/arm-gic.h>
159 #include <dt-bindings/gpio/gpio.h>
161 gpmc: memory-controller@50000000 {
162 compatible = "ti,am3352-gpmc";
163 reg = <0x50000000 0x2000>;
165 clocks = <&l3s_clkctrl>;
170 gpmc,num-waitpins = <2>;
171 #address-cells = <2>;
173 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
174 interrupt-controller;
175 #interrupt-cells = <2>;
180 compatible = "ti,omap2-nand";
182 interrupt-parent = <&gpmc>;
183 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
184 <1 IRQ_TYPE_NONE>; /* termcount */
185 ti,nand-xfer-type = "prefetch-dma";
186 ti,nand-ecc-opt = "bch16";
188 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */