1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC SROM Controller driver
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The SROM controller can be used to attach external peripherals. In this case
14 extra properties, describing the bus behind it, should be specified.
19 - const: samsung,exynos4210-srom
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
36 Up to four banks are supported.
39 "^.*@[0-3],[a-f0-9]+$":
42 The actual device nodes should be added as subnodes to the SROMc node.
43 These subnodes, in addition to regular device specification, should
44 contain the following properties, describing configuration
45 of the relevant SROM bank.
50 Bank number, base address (relative to start of the bank) and size
51 of the memory mapped for the device. Note that base address will be
52 typically 0 as this is the start of the bank.
58 Data width in bytes (1 or 2). If omitted, default of 1 is used.
60 samsung,srom-page-mode:
62 If page mode is set, 4 data page mode will be configured,
63 else normal (1 data) page mode will be set.
67 $ref: /schemas/types.yaml#/definitions/uint32-array
72 Array of 6 integers, specifying bank timings in the following order:
73 Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
74 Each value is specified in cycles and has the following meaning
76 Tacp: Page mode access cycle at Page mode (0 - 15)
77 Tcah: Address holding time after CSn (0 - 15)
78 Tcoh: Chip selection hold on OEn (0 - 15)
79 Tacc: Access cycle (0 - 31, the actual time is N + 1)
80 Tcos: Chip selection set-up before OEn (0 - 15)
81 Tacs: Address set-up before CSn (0 - 15)
91 additionalProperties: false
95 // Example: basic definition, no banks are configured
96 memory-controller@12560000 {
97 compatible = "samsung,exynos4210-srom";
98 reg = <0x12560000 0x14>;
102 // Example: SROMc with SMSC911x ethernet chip on bank 3
103 memory-controller@12570000 {
104 #address-cells = <2>;
106 ranges = <0 0 0x04000000 0x20000 // Bank0
107 1 0 0x05000000 0x20000 // Bank1
108 2 0 0x06000000 0x20000 // Bank2
109 3 0 0x07000000 0x20000>; // Bank3
111 compatible = "samsung,exynos4210-srom";
112 reg = <0x12570000 0x14>;
115 compatible = "smsc,lan9115";
116 reg = <3 0 0x10000>; // Bank 3, offset = 0
118 interrupt-parent = <&gpx0>;
122 smsc,force-internal-phy;
124 samsung,srom-page-mode;
125 samsung,srom-timing = <9 12 1 9 1 1>;