1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
23 - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
31 $ref: /schemas/types.yaml#/definitions/uint32
33 Manufacturer ID value read from Mode Register 5. The property is
34 deprecated, manufacturer should be derived from the compatible.
42 $ref: /schemas/types.yaml#/definitions/uint32
45 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
49 $ref: /schemas/types.yaml#/definitions/uint32
52 CKE minimum pulse width during SELF REFRESH (low pulse width during
53 SELF REFRESH) in terms of number of clock cycles.
56 $ref: /schemas/types.yaml#/definitions/uint32
59 DQS output data access time from CK_t/CK_c in terms of number of clock
63 $ref: /schemas/types.yaml#/definitions/uint32
66 Four-bank activate window in terms of number of clock cycles.
69 $ref: /schemas/types.yaml#/definitions/uint32
72 Mode register set command delay in terms of number of clock cycles.
75 $ref: /schemas/types.yaml#/definitions/uint32
78 Additional READ-to-READ delay in chip-to-chip cases in terms of number
82 $ref: /schemas/types.yaml#/definitions/uint32
85 Row active time in terms of number of clock cycles.
88 $ref: /schemas/types.yaml#/definitions/uint32
91 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
94 $ref: /schemas/types.yaml#/definitions/uint32
97 RAS-to-CAS delay in terms of number of clock cycles.
100 $ref: /schemas/types.yaml#/definitions/uint32
103 Refresh Cycle time in terms of number of clock cycles.
106 $ref: /schemas/types.yaml#/definitions/uint32
109 READ data latency in terms of number of clock cycles.
112 $ref: /schemas/types.yaml#/definitions/uint32
115 Row precharge time (all banks) in terms of number of clock cycles.
118 $ref: /schemas/types.yaml#/definitions/uint32
121 Row precharge time (single banks) in terms of number of clock cycles.
124 $ref: /schemas/types.yaml#/definitions/uint32
127 Active bank A to active bank B in terms of number of clock cycles.
130 $ref: /schemas/types.yaml#/definitions/uint32
133 Internal READ to PRECHARGE command delay in terms of number of clock
137 $ref: /schemas/types.yaml#/definitions/uint32
140 Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
144 $ref: /schemas/types.yaml#/definitions/uint32
147 WRITE data latency in terms of number of clock cycles.
150 $ref: /schemas/types.yaml#/definitions/uint32
153 WRITE recovery time in terms of number of clock cycles.
156 $ref: /schemas/types.yaml#/definitions/uint32
159 Internal WRITE-to-READ command delay in terms of number of clock cycles.
162 $ref: /schemas/types.yaml#/definitions/uint32
165 Exit power-down to next valid command delay in terms of number of clock
169 $ref: /schemas/types.yaml#/definitions/uint32
172 SELF REFRESH exit to next valid command delay in terms of number of clock
176 "^timings((-[0-9])+|(@[0-9a-f]+))?$":
177 $ref: jedec,lpddr3-timings.yaml
179 The lpddr3 node may have one or more child nodes with timings.
180 Each timing node provides AC timing parameters of the device for a given
181 speed-bin. The user may provide the timings for as many speed-bins as is
189 unevaluatedProperties: false
194 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
199 tCKESR-min-tck = <2>;
200 tDQSCK-min-tck = <5>;
203 tR2R-C2C-min-tck = <0>;
213 tW2W-C2C-min-tck = <0>;
221 compatible = "jedec,lpddr3-timings";
222 max-freq = <800000000>;
223 min-freq = <100000000>;