Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: LPDDR channel with chip/rank topology description
   8
   9 description:
  10   An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
  11   CK, etc.) that connect one or more LPDDR chips to a host system. The main
  12   purpose of this node is to overall LPDDR topology of the system, including the
  13   amount of individual LPDDR chips and the ranks per chip.
  14
  15 maintainers:
  16   - Julius Werner <jwerner@chromium.org>
  17
  18 properties:
  19   compatible:
  20     enum:
  21       - jedec,lpddr2-channel
  22       - jedec,lpddr3-channel
  23       - jedec,lpddr4-channel
  24       - jedec,lpddr5-channel
  25
  26   io-width:
  27     description:
  28       The number of DQ pins in the channel. If this number is different
  29       from (a multiple of) the io-width of the LPDDR chip, that means that
  30       multiple instances of that type of chip are wired in parallel on this
  31       channel (with the channel's DQ pins split up between the different
  32       chips, and the CA, CS, etc. pins of the different chips all shorted
  33       together).  This means that the total physical memory controlled by a
  34       channel is equal to the sum of the densities of each rank on the
  35       connected LPDDR chip, times the io-width of the channel divided by
  36       the io-width of the LPDDR chip.
  37     enum:
  38       - 8
  39       - 16
  40       - 32
  41       - 64
  42       - 128
  43
  44   "#address-cells":
  45     const: 1
  46
  47   "#size-cells":
  48     const: 0
  49
  50 patternProperties:
  51   "^rank@[0-9]+$":
  52     type: object
  53     description:
  54       Each physical LPDDR chip may have one or more ranks. Ranks are
  55       internal but fully independent sub-units of the chip. Each LPDDR bus
  56       transaction on the channel targets exactly one rank, based on the
  57       state of the CS pins. Different ranks may have different densities and
  58       timing requirements.
  59     required:
  60       - reg
  61
  62 allOf:
  63   - if:
  64       properties:
  65         compatible:
  66           contains:
  67             const: jedec,lpddr2-channel
  68     then:
  69       patternProperties:
  70         "^rank@[0-9]+$":
  71           $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
  72   - if:
  73       properties:
  74         compatible:
  75           contains:
  76             const: jedec,lpddr3-channel
  77     then:
  78       patternProperties:
  79         "^rank@[0-9]+$":
  80           $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
  81   - if:
  82       properties:
  83         compatible:
  84           contains:
  85             const: jedec,lpddr4-channel
  86     then:
  87       patternProperties:
  88         "^rank@[0-9]+$":
  89           $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
  90   - if:
  91       properties:
  92         compatible:
  93           contains:
  94             const: jedec,lpddr5-channel
  95     then:
  96       patternProperties:
  97         "^rank@[0-9]+$":
  98           $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
  99
 100 required:
 101   - compatible
 102   - io-width
 103   - "#address-cells"
 104   - "#size-cells"
 105
 106 additionalProperties: false
 107
 108 examples:
 109   - |
 110     lpddr-channel0 {
 111       #address-cells = <1>;
 112       #size-cells = <0>;
 113       compatible = "jedec,lpddr3-channel";
 114       io-width = <32>;
 115
 116       rank@0 {
 117         compatible = "lpddr3-ff,0100", "jedec,lpddr3";
 118         reg = <0>;
 119         density = <8192>;
 120         io-width = <16>;
 121         revision-id = <1 0>;
 122       };
 123     };
 124
 125     lpddr-channel1 {
 126       #address-cells = <1>;
 127       #size-cells = <0>;
 128       compatible = "jedec,lpddr4-channel";
 129       io-width = <32>;
 130
 131       rank@0 {
 132         compatible = "lpddr4-05,0301", "jedec,lpddr4";
 133         reg = <0>;
 134         density = <4096>;
 135         io-width = <32>;
 136         revision-id = <3 1>;
 137       };
 138
 139       rank@1 {
 140         compatible = "lpddr4-05,0301", "jedec,lpddr4";
 141         reg = <1>;
 142         density = <2048>;
 143         io-width = <32>;
 144         revision-id = <3 1>;
 145       };
 146     };