1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-csis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 - samsung,s5pv210-csis
17 - samsung,exynos4210-csis
18 - samsung,exynos4212-csis
19 - samsung,exynos5250-csis
31 $ref: /schemas/types.yaml#/definitions/uint32
34 Number of data lines supported.
47 The IP's main (system bus) clock frequency in Hz.
63 description: MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V).
66 description: MIPI CSIS Core voltage supply (e.g. 1.1V).
70 $ref: /schemas/graph.yaml#/$defs/port-base
71 additionalProperties: false
80 $ref: video-interfaces.yaml#
81 unevaluatedProperties: false
88 samsung,csis-hs-settle:
89 $ref: /schemas/types.yaml#/definitions/uint32
90 description: Differential receiver (HS-RX) settle time.
95 CSI-2 wrapper clock selection. If this property is present external clock
96 from CMU will be used, or the bus clock if it's not specified.
128 additionalProperties: false
132 #include <dt-bindings/clock/exynos4.h>
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
136 compatible = "samsung,exynos4210-csis";
137 reg = <0x11890000 0x4000>;
138 clocks = <&clock CLK_CSIS1>,
139 <&clock CLK_SCLK_CSIS1>;
140 clock-names = "csis", "sclk_csis";
141 assigned-clocks = <&clock CLK_MOUT_CSIS1>,
142 <&clock CLK_SCLK_CSIS1>;
143 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
144 assigned-clock-rates = <0>, <176000000>;
146 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
149 power-domains = <&pd_cam>;
150 phys = <&mipi_phy 2>;
153 vddcore-supply = <&ldo8_reg>;
154 vddio-supply = <&ldo10_reg>;
156 #address-cells = <1>;
159 /* Camera D (4) MIPI CSI-2 (CSIS1) */
164 remote-endpoint = <&is_s5k6a3_ep>;
166 samsung,csis-hs-settle = <18>;