1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Image Signal Processing unit v1
10 - Helen Koike <helen.koike@collabora.com>
13 Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14 which contains image processing, scaling, and compression functions.
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
39 - description: ISP clock
40 - description: ISP AXI clock
41 - description: ISP AHB clock
43 - description: ISP Pixel clock
60 description: phandle for the PHY port
69 $ref: /schemas/graph.yaml#/properties/ports
73 $ref: /schemas/graph.yaml#/$defs/port-base
74 unevaluatedProperties: false
75 description: connection point for sensors at MIPI-DPHY RX0
79 $ref: video-interfaces.yaml#
80 unevaluatedProperties: false
88 $ref: /schemas/graph.yaml#/$defs/port-base
89 unevaluatedProperties: false
90 description: connection point for input on the parallel interface
94 $ref: video-interfaces.yaml#
95 unevaluatedProperties: false
127 const: rockchip,rk3399-cif-isp
141 const: rockchip,px30-cif-isp
146 additionalProperties: false
151 #include <dt-bindings/clock/rk3399-cru.h>
152 #include <dt-bindings/interrupt-controller/arm-gic.h>
153 #include <dt-bindings/power/rk3399-power.h>
156 #address-cells = <2>;
159 isp0: isp0@ff910000 {
160 compatible = "rockchip,rk3399-cif-isp";
161 reg = <0x0 0xff910000 0x0 0x4000>;
162 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
163 clocks = <&cru SCLK_ISP0>,
164 <&cru ACLK_ISP0_WRAPPER>,
165 <&cru HCLK_ISP0_WRAPPER>;
166 clock-names = "isp", "aclk", "hclk";
167 iommus = <&isp0_mmu>;
170 power-domains = <&power RK3399_PD_ISP0>;
173 #address-cells = <1>;
178 #address-cells = <1>;
181 mipi_in_wcam: endpoint@0 {
183 remote-endpoint = <&wcam_out>;
187 mipi_in_ucam: endpoint@1 {
189 remote-endpoint = <&ucam_out>;
197 #address-cells = <1>;
201 compatible = "ovti,ov5695";
206 remote-endpoint = <&mipi_in_wcam>;
213 compatible = "ovti,ov2685";
218 remote-endpoint = <&mipi_in_ucam>;
228 #include <dt-bindings/interrupt-controller/arm-gic.h>
229 #include <dt-bindings/power/px30-power.h>
232 #address-cells = <2>;
236 compatible = "rockchip,px30-cif-isp";
237 reg = <0x0 0xff4a0000 0x0 0x8000>;
238 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "isp", "mi", "mipi";
242 clocks = <&cru SCLK_ISP0>,
243 <&cru ACLK_ISP0_WRAPPER>,
244 <&cru HCLK_ISP0_WRAPPER>,
245 <&cru PCLK_ISP1_WRAPPER>;
246 clock-names = "isp", "aclk", "hclk", "pclk";
250 power-domains = <&power PX30_PD_VI>;
253 #address-cells = <1>;
258 #address-cells = <1>;
261 mipi_in_ucam1: endpoint@0 {
263 remote-endpoint = <&ucam1_out>;
271 #address-cells = <1>;
275 compatible = "ovti,ov5647";
277 clocks = <&cru SCLK_CIF_OUT>;
280 ucam1_out: endpoint {
281 remote-endpoint = <&mipi_in_ucam1>;