1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Image Signal Processing unit v1
10 - Helen Koike <helen.koike@collabora.com>
13 Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
14 which contains image processing, scaling, and compression functions.
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
39 - description: ISP clock
40 - description: ISP AXI clock
41 - description: ISP AHB clock
43 - description: ISP Pixel clock
60 description: phandle for the PHY port
69 $ref: /schemas/graph.yaml#/properties/ports
73 $ref: /schemas/graph.yaml#/$defs/port-base
74 unevaluatedProperties: false
75 description: connection point for sensors at MIPI-DPHY RX0
79 $ref: video-interfaces.yaml#
80 unevaluatedProperties: false
88 $ref: /schemas/graph.yaml#/$defs/port-base
89 unevaluatedProperties: false
90 description: connection point for input on the parallel interface
97 $ref: video-interfaces.yaml#
98 unevaluatedProperties: false
126 const: rockchip,rk3399-cif-isp
140 const: rockchip,px30-cif-isp
145 additionalProperties: false
150 #include <dt-bindings/clock/rk3399-cru.h>
151 #include <dt-bindings/interrupt-controller/arm-gic.h>
152 #include <dt-bindings/power/rk3399-power.h>
155 #address-cells = <2>;
158 isp0: isp0@ff910000 {
159 compatible = "rockchip,rk3399-cif-isp";
160 reg = <0x0 0xff910000 0x0 0x4000>;
161 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
162 clocks = <&cru SCLK_ISP0>,
163 <&cru ACLK_ISP0_WRAPPER>,
164 <&cru HCLK_ISP0_WRAPPER>;
165 clock-names = "isp", "aclk", "hclk";
166 iommus = <&isp0_mmu>;
169 power-domains = <&power RK3399_PD_ISP0>;
172 #address-cells = <1>;
177 #address-cells = <1>;
180 mipi_in_wcam: endpoint@0 {
182 remote-endpoint = <&wcam_out>;
186 mipi_in_ucam: endpoint@1 {
188 remote-endpoint = <&ucam_out>;
196 #address-cells = <1>;
200 compatible = "ovti,ov5695";
202 clocks = <&cru SCLK_TESTCLKOUT1>;
206 remote-endpoint = <&mipi_in_wcam>;
213 compatible = "ovti,ov2685";
216 clocks = <&cru SCLK_TESTCLKOUT1>;
217 clock-names = "xvclk";
219 avdd-supply = <&pp2800_cam>;
220 dovdd-supply = <&pp1800>;
221 dvdd-supply = <&pp1800>;
225 remote-endpoint = <&mipi_in_ucam>;
235 #include <dt-bindings/interrupt-controller/arm-gic.h>
236 #include <dt-bindings/power/px30-power.h>
239 #address-cells = <2>;
243 compatible = "rockchip,px30-cif-isp";
244 reg = <0x0 0xff4a0000 0x0 0x8000>;
245 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "isp", "mi", "mipi";
249 clocks = <&cru SCLK_ISP0>,
250 <&cru ACLK_ISP0_WRAPPER>,
251 <&cru HCLK_ISP0_WRAPPER>,
252 <&cru PCLK_ISP1_WRAPPER>;
253 clock-names = "isp", "aclk", "hclk", "pclk";
257 power-domains = <&power PX30_PD_VI>;
260 #address-cells = <1>;
265 #address-cells = <1>;
268 mipi_in_ucam1: endpoint@0 {
270 remote-endpoint = <&ucam1_out>;
278 #address-cells = <1>;
282 compatible = "ovti,ov5647";
284 clocks = <&cru SCLK_CIF_OUT>;
287 ucam1_out: endpoint {
288 remote-endpoint = <&mipi_in_ucam1>;