1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/renesas,vsp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VSP Video Processing Engine
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
21 - renesas,r9a07g044-vsp2 # RZ/G2L
22 - renesas,vsp1 # R-Car Gen2 and RZ/G1
23 - renesas,vsp2 # R-Car Gen3 and RZ/G2
26 - renesas,r9a07g054-vsp2 # RZ/V2L
27 - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback
45 $ref: /schemas/types.yaml#/definitions/phandle
47 A phandle referencing the FCP that handles memory accesses for the VSP.
57 additionalProperties: false
76 const: renesas,r9a07g044-vsp2
81 - description: Main clock
82 - description: Register access clock
83 - description: Video clock
98 # R8A7790 (R-Car H2) VSP1-S
100 #include <dt-bindings/clock/renesas-cpg-mssr.h>
101 #include <dt-bindings/interrupt-controller/arm-gic.h>
102 #include <dt-bindings/power/r8a7790-sysc.h>
105 compatible = "renesas,vsp1";
106 reg = <0xfe928000 0x8000>;
107 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&cpg CPG_MOD 131>;
109 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
113 # R8A77951 (R-Car H3) VSP2-BC
115 #include <dt-bindings/clock/renesas-cpg-mssr.h>
116 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 #include <dt-bindings/power/r8a7795-sysc.h>
120 compatible = "renesas,vsp2";
121 reg = <0xfe920000 0x8000>;
122 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&cpg CPG_MOD 624>;
124 power-domains = <&sysc R8A7795_PD_A3VP>;
127 renesas,fcp = <&fcpvb1>;