1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm CAMSS ISP
11 - Robert Foss <robert.foss@linaro.org>
14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
18 const: qcom,sm8250-camss
30 - const: camnoc_axi_src
34 - const: csiphy0_timer
36 - const: csiphy1_timer
38 - const: csiphy2_timer
40 - const: csiphy3_timer
42 - const: csiphy4_timer
44 - const: csiphy5_timer
61 - const: vfe_lite_cphy_rx
62 - const: vfe_lite_csid
96 - const: cam_hf_0_mnoc
97 - const: cam_sf_0_mnoc
98 - const: cam_sf_icp_mnoc
102 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
103 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
104 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
107 $ref: /schemas/graph.yaml#/properties/ports
114 $ref: /schemas/graph.yaml#/$defs/port-base
115 unevaluatedProperties: false
117 Input port for receiving CSI data.
121 $ref: video-interfaces.yaml#
122 unevaluatedProperties: false
137 $ref: /schemas/graph.yaml#/$defs/port-base
138 unevaluatedProperties: false
140 Input port for receiving CSI data.
144 $ref: video-interfaces.yaml#
145 unevaluatedProperties: false
160 $ref: /schemas/graph.yaml#/$defs/port-base
161 unevaluatedProperties: false
163 Input port for receiving CSI data.
167 $ref: video-interfaces.yaml#
168 unevaluatedProperties: false
183 $ref: /schemas/graph.yaml#/$defs/port-base
184 unevaluatedProperties: false
186 Input port for receiving CSI data.
190 $ref: video-interfaces.yaml#
191 unevaluatedProperties: false
206 $ref: /schemas/graph.yaml#/$defs/port-base
207 unevaluatedProperties: false
209 Input port for receiving CSI data.
213 $ref: video-interfaces.yaml#
214 unevaluatedProperties: false
229 $ref: /schemas/graph.yaml#/$defs/port-base
230 unevaluatedProperties: false
232 Input port for receiving CSI data.
236 $ref: video-interfaces.yaml#
237 unevaluatedProperties: false
270 Phandle to a regulator supply to PHY core block.
274 Phandle to 1.8V regulator supply to PHY refclk pll block.
291 additionalProperties: false
295 #include <dt-bindings/interrupt-controller/arm-gic.h>
296 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
297 #include <dt-bindings/interconnect/qcom,sm8250.h>
298 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
299 #include <dt-bindings/power/qcom-rpmpd.h>
302 #address-cells = <2>;
305 camss: camss@ac6a000 {
306 compatible = "qcom,sm8250-camss";
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
317 <0 0xacdb200 0 0x2200>;
318 reg-names = "csiphy0",
329 vdda-phy-supply = <&vreg_l5a_0p88>;
330 vdda-pll-supply = <&vreg_l9a_1p2>;
332 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "csiphy0",
361 power-domains = <&camcc IFE_0_GDSC>,
363 <&camcc TITAN_TOP_GDSC>;
365 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
366 <&gcc GCC_CAMERA_HF_AXI_CLK>,
367 <&gcc GCC_CAMERA_SF_AXI_CLK>,
368 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
369 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
370 <&camcc CAM_CC_CORE_AHB_CLK>,
371 <&camcc CAM_CC_CPAS_AHB_CLK>,
372 <&camcc CAM_CC_CSIPHY0_CLK>,
373 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
374 <&camcc CAM_CC_CSIPHY1_CLK>,
375 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
376 <&camcc CAM_CC_CSIPHY2_CLK>,
377 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
378 <&camcc CAM_CC_CSIPHY3_CLK>,
379 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
380 <&camcc CAM_CC_CSIPHY4_CLK>,
381 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
382 <&camcc CAM_CC_CSIPHY5_CLK>,
383 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
384 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
385 <&camcc CAM_CC_IFE_0_AHB_CLK>,
386 <&camcc CAM_CC_IFE_0_AXI_CLK>,
387 <&camcc CAM_CC_IFE_0_CLK>,
388 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
389 <&camcc CAM_CC_IFE_0_CSID_CLK>,
390 <&camcc CAM_CC_IFE_0_AREG_CLK>,
391 <&camcc CAM_CC_IFE_1_AHB_CLK>,
392 <&camcc CAM_CC_IFE_1_AXI_CLK>,
393 <&camcc CAM_CC_IFE_1_CLK>,
394 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
395 <&camcc CAM_CC_IFE_1_CSID_CLK>,
396 <&camcc CAM_CC_IFE_1_AREG_CLK>,
397 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
398 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
399 <&camcc CAM_CC_IFE_LITE_CLK>,
400 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
401 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
402 clock-names = "cam_ahb_clk",
440 iommus = <&apps_smmu 0x800 0x400>,
441 <&apps_smmu 0x801 0x400>,
442 <&apps_smmu 0x840 0x400>,
443 <&apps_smmu 0x841 0x400>,
444 <&apps_smmu 0xC00 0x400>,
445 <&apps_smmu 0xC01 0x400>,
446 <&apps_smmu 0xC40 0x400>,
447 <&apps_smmu 0xC41 0x400>;
449 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
450 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
451 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
452 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
453 interconnect-names = "cam_ahb",
459 #address-cells = <1>;