1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm CAMSS ISP
11 - Robert Foss <robert.foss@linaro.org>
14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
18 const: qcom,sdm845-camss
36 - const: csiphy0_timer
37 - const: csiphy0_timer_src
39 - const: csiphy1_timer
40 - const: csiphy1_timer_src
42 - const: csiphy2_timer
43 - const: csiphy2_timer_src
45 - const: csiphy3_timer
46 - const: csiphy3_timer_src
47 - const: gcc_camera_ahb
48 - const: gcc_camera_axi
60 - const: vfe_lite_cphy_rx
85 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
86 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
87 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
90 $ref: /schemas/graph.yaml#/properties/ports
97 $ref: /schemas/graph.yaml#/$defs/port-base
98 unevaluatedProperties: false
100 Input port for receiving CSI data.
104 $ref: video-interfaces.yaml#
105 unevaluatedProperties: false
116 $ref: /schemas/graph.yaml#/$defs/port-base
117 unevaluatedProperties: false
119 Input port for receiving CSI data.
123 $ref: video-interfaces.yaml#
124 unevaluatedProperties: false
135 $ref: /schemas/graph.yaml#/$defs/port-base
136 unevaluatedProperties: false
138 Input port for receiving CSI data.
142 $ref: video-interfaces.yaml#
143 unevaluatedProperties: false
154 $ref: /schemas/graph.yaml#/$defs/port-base
155 unevaluatedProperties: false
157 Input port for receiving CSI data.
161 $ref: video-interfaces.yaml#
162 unevaluatedProperties: false
191 Phandle to a regulator supply to PHY core block.
195 Phandle to 1.8V regulator supply to PHY refclk pll block.
210 additionalProperties: false
214 #include <dt-bindings/interrupt-controller/arm-gic.h>
215 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
216 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
219 #address-cells = <2>;
222 camss: camss@a00000 {
223 compatible = "qcom,sdm845-camss";
225 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
226 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
227 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
228 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
229 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
230 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
231 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
232 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
233 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
234 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
235 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
236 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
237 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
238 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
239 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
240 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
241 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
242 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
243 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
244 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
245 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
246 <&gcc GCC_CAMERA_AHB_CLK>,
247 <&gcc GCC_CAMERA_AXI_CLK>,
248 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
249 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
250 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
251 <&clock_camcc CAM_CC_IFE_0_CLK>,
252 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
253 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
254 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
255 <&clock_camcc CAM_CC_IFE_1_CLK>,
256 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
257 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
258 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
259 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
260 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
262 clock-names = "camnoc_axi",
299 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "csid0",
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
326 power-domains = <&clock_camcc IFE_0_GDSC>,
327 <&clock_camcc IFE_1_GDSC>,
328 <&clock_camcc TITAN_TOP_GDSC>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
335 <0 0xac67000 0 0x1000>,
336 <0 0xac68000 0 0x1000>,
337 <0 0xacaf000 0 0x4000>,
338 <0 0xacb6000 0 0x4000>,
339 <0 0xacc4000 0 0x4000>;
352 vdda-phy-supply = <&vreg_l1a_0p875>;
353 vdda-pll-supply = <&vreg_l26a_1p2>;
356 #address-cells = <1>;