1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm CAMSS ISP
11 - Robert Foss <robert.foss@linaro.org>
12 - Todor Tomov <todor.too@gmail.com>
15 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
19 const: qcom,msm8996-camss
29 - const: csiphy0_timer
30 - const: csiphy1_timer
31 - const: csiphy2_timer
86 - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
87 - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
90 $ref: /schemas/graph.yaml#/properties/ports
97 $ref: /schemas/graph.yaml#/$defs/port-base
98 unevaluatedProperties: false
100 Input port for receiving CSI data.
104 $ref: video-interfaces.yaml#
105 unevaluatedProperties: false
110 An array of physical data lanes indexes.
111 Position of an entry determines the logical
112 lane number, while the value of an entry
113 indicates physical lane index. Lane swapping
114 is supported. Physical lane indexes are;
123 $ref: /schemas/graph.yaml#/$defs/port-base
124 unevaluatedProperties: false
126 Input port for receiving CSI data.
130 $ref: video-interfaces.yaml#
131 unevaluatedProperties: false
142 $ref: /schemas/graph.yaml#/$defs/port-base
143 unevaluatedProperties: false
145 Input port for receiving CSI data.
149 $ref: video-interfaces.yaml#
150 unevaluatedProperties: false
161 $ref: /schemas/graph.yaml#/$defs/port-base
162 unevaluatedProperties: false
164 Input port for receiving CSI data.
168 $ref: video-interfaces.yaml#
169 unevaluatedProperties: false
186 - const: csiphy0_clk_mux
188 - const: csiphy1_clk_mux
190 - const: csiphy2_clk_mux
202 Definition of the regulator used as analog power supply.
216 additionalProperties: false
220 #include <dt-bindings/interrupt-controller/arm-gic.h>
221 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
222 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
224 camss: camss@a34000 {
225 compatible = "qcom,msm8996-camss";
227 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
228 <&mmcc CAMSS_ISPIF_AHB_CLK>,
229 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
230 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
231 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
232 <&mmcc CAMSS_CSI0_AHB_CLK>,
233 <&mmcc CAMSS_CSI0_CLK>,
234 <&mmcc CAMSS_CSI0PHY_CLK>,
235 <&mmcc CAMSS_CSI0PIX_CLK>,
236 <&mmcc CAMSS_CSI0RDI_CLK>,
237 <&mmcc CAMSS_CSI1_AHB_CLK>,
238 <&mmcc CAMSS_CSI1_CLK>,
239 <&mmcc CAMSS_CSI1PHY_CLK>,
240 <&mmcc CAMSS_CSI1PIX_CLK>,
241 <&mmcc CAMSS_CSI1RDI_CLK>,
242 <&mmcc CAMSS_CSI2_AHB_CLK>,
243 <&mmcc CAMSS_CSI2_CLK>,
244 <&mmcc CAMSS_CSI2PHY_CLK>,
245 <&mmcc CAMSS_CSI2PIX_CLK>,
246 <&mmcc CAMSS_CSI2RDI_CLK>,
247 <&mmcc CAMSS_CSI3_AHB_CLK>,
248 <&mmcc CAMSS_CSI3_CLK>,
249 <&mmcc CAMSS_CSI3PHY_CLK>,
250 <&mmcc CAMSS_CSI3PIX_CLK>,
251 <&mmcc CAMSS_CSI3RDI_CLK>,
252 <&mmcc CAMSS_AHB_CLK>,
253 <&mmcc CAMSS_VFE0_CLK>,
254 <&mmcc CAMSS_CSI_VFE0_CLK>,
255 <&mmcc CAMSS_VFE0_AHB_CLK>,
256 <&mmcc CAMSS_VFE0_STREAM_CLK>,
257 <&mmcc CAMSS_VFE1_CLK>,
258 <&mmcc CAMSS_CSI_VFE1_CLK>,
259 <&mmcc CAMSS_VFE1_AHB_CLK>,
260 <&mmcc CAMSS_VFE1_STREAM_CLK>,
261 <&mmcc CAMSS_VFE_AHB_CLK>,
262 <&mmcc CAMSS_VFE_AXI_CLK>;
264 clock-names = "top_ahb",
301 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
302 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
303 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
304 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
305 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
306 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
307 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
308 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
309 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
310 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
312 interrupt-names = "csiphy0",
323 iommus = <&vfe_smmu 0>,
328 power-domains = <&mmcc VFE0_GDSC>,
331 reg = <0x00a34000 0x1000>,
346 reg-names = "csiphy0",
361 vdda-supply = <®_2v8>;
364 #address-cells = <1>;