1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
16 compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
17 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
20 completely wrapped by the CSIS and doesn't expose a control interface of its
21 own. This binding thus covers both IP cores.
28 - fsl,imx8mm-mipi-csi2
31 - fsl,imx8mp-mipi-csi2
32 - const: fsl,imx8mm-mipi-csi2
43 - description: The peripheral clock (a.k.a. APB clock)
44 - description: The external clock (optionally used as the pixel clock)
45 - description: The MIPI D-PHY clock
46 - description: The AXI clock
60 description: The MIPI D-PHY digital power supply
64 - description: MIPI D-PHY slave reset
67 description: The desired external clock ("wrap") frequency, in Hz
71 $ref: /schemas/graph.yaml#/properties/ports
75 $ref: /schemas/graph.yaml#/$defs/port-base
76 unevaluatedProperties: false
78 Input port node, single endpoint describing the CSI-2 transmitter.
82 $ref: video-interfaces.yaml#
83 unevaluatedProperties: false
88 Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
100 $ref: /schemas/graph.yaml#/properties/port
113 additionalProperties: false
120 const: fsl,imx7-mipi-csi2
136 #include <dt-bindings/clock/imx7d-clock.h>
137 #include <dt-bindings/interrupt-controller/arm-gic.h>
138 #include <dt-bindings/interrupt-controller/irq.h>
139 #include <dt-bindings/reset/imx7-reset.h>
142 compatible = "fsl,imx7-mipi-csi2";
143 reg = <0x30750000 0x10000>;
144 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
147 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
148 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
149 clock-names = "pclk", "wrap", "phy";
150 clock-frequency = <166000000>;
152 power-domains = <&pgc_mipi_phy>;
153 phy-supply = <®_1p0d>;
154 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
157 #address-cells = <1>;
163 mipi_from_sensor: endpoint {
164 remote-endpoint = <&ov2680_to_mipi>;
172 mipi_vc0_to_csi_mux: endpoint {
173 remote-endpoint = <&csi_mux_from_mipi_vc0>;
180 #include <dt-bindings/clock/imx8mm-clock.h>
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/interrupt-controller/irq.h>
185 compatible = "fsl,imx8mm-mipi-csi2";
186 reg = <0x32e30000 0x1000>;
187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
188 clock-frequency = <333000000>;
189 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
190 <&clk IMX8MM_CLK_CSI1_ROOT>,
191 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
192 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
193 clock-names = "pclk", "wrap", "phy", "axi";
194 power-domains = <&mipi_pd>;
197 #address-cells = <1>;
203 imx8mm_mipi_csi_in: endpoint {
204 remote-endpoint = <&imx477_out>;
205 data-lanes = <1 2 3 4>;
212 imx8mm_mipi_csi_out: endpoint {
213 remote-endpoint = <&csi_in>;