1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
16 compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
17 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
20 completely wrapped by the CSIS and doesn't expose a control interface of its
21 own. This binding thus covers both IP cores.
27 - fsl,imx8mm-mipi-csi2
38 - description: The peripheral clock (a.k.a. APB clock)
39 - description: The external clock (optionally used as the pixel clock)
40 - description: The MIPI D-PHY clock
41 - description: The AXI clock
55 description: The MIPI D-PHY digital power supply
59 - description: MIPI D-PHY slave reset
62 description: The desired external clock ("wrap") frequency, in Hz
66 $ref: /schemas/graph.yaml#/properties/ports
70 $ref: /schemas/graph.yaml#/$defs/port-base
71 unevaluatedProperties: false
73 Input port node, single endpoint describing the CSI-2 transmitter.
77 $ref: video-interfaces.yaml#
78 unevaluatedProperties: false
83 Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
95 $ref: /schemas/graph.yaml#/properties/port
108 additionalProperties: false
115 const: fsl,imx7-mipi-csi2
131 #include <dt-bindings/clock/imx7d-clock.h>
132 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/interrupt-controller/irq.h>
134 #include <dt-bindings/reset/imx7-reset.h>
137 compatible = "fsl,imx7-mipi-csi2";
138 reg = <0x30750000 0x10000>;
139 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
142 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
143 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
144 clock-names = "pclk", "wrap", "phy";
145 clock-frequency = <166000000>;
147 power-domains = <&pgc_mipi_phy>;
148 phy-supply = <®_1p0d>;
149 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
152 #address-cells = <1>;
158 mipi_from_sensor: endpoint {
159 remote-endpoint = <&ov2680_to_mipi>;
167 mipi_vc0_to_csi_mux: endpoint {
168 remote-endpoint = <&csi_mux_from_mipi_vc0>;
175 #include <dt-bindings/clock/imx8mm-clock.h>
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/interrupt-controller/irq.h>
180 compatible = "fsl,imx8mm-mipi-csi2";
181 reg = <0x32e30000 0x1000>;
182 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <333000000>;
184 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
185 <&clk IMX8MM_CLK_CSI1_ROOT>,
186 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
187 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
188 clock-names = "pclk", "wrap", "phy", "axi";
189 power-domains = <&mipi_pd>;
192 #address-cells = <1>;
198 imx8mm_mipi_csi_in: endpoint {
199 remote-endpoint = <&imx477_out>;
200 data-lanes = <1 2 3 4>;
207 imx8mm_mipi_csi_out: endpoint {
208 remote-endpoint = <&csi_in>;