1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip CSI2 Demux Controller (CSI2DC)
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
15 CSI2DC is a hardware block that receives incoming data from either from an
16 IDI interface or from a parallel bus interface.
17 It filters IDI packets based on their data type and virtual channel
18 identifier, then converts the byte stream to a pixel stream into a cross
19 clock domain towards a parallel interface that can be read by a sensor
21 IDI interface is Synopsys proprietary.
22 CSI2DC can act a simple bypass bridge if the incoming data is coming from
25 CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
26 is connected at the output to a sensor controller and the data pipe is
27 accessible as a DMA slave port to a DMA controller.
29 CSI2DC supports a single 'port' node as a sink port with either Synopsys
30 32-bit IDI interface or a parallel interface.
32 CSI2DC supports one 'port' node as source port with parallel interface.
33 This is called video pipe.
34 This port has an 'endpoint' that can be connected to a sink port of another
35 controller (next in pipeline).
37 CSI2DC also supports direct access to the data through AHB, via DMA channel,
39 For data pipe to be available, a dma controller and a dma channel must be
44 const: microchip,sama7g5-csi2dc
55 CSI2DC must have two clocks to function correctly. One clock is the
56 peripheral clock for the inside functionality of the hardware block.
57 This is named 'pclk'. The second clock must be the cross domain clock,
58 in which CSI2DC will perform clock crossing. This clock must be fed
59 by the next controller in pipeline, which usually is a sensor controller.
60 Normally this clock should be given by this sensor controller who
61 is also a clock source. This clock is named 'scck', sensor controller clock.
73 $ref: /schemas/graph.yaml#/properties/ports
77 $ref: /schemas/graph.yaml#/$defs/port-base
78 unevaluatedProperties: false
80 Input port node, single endpoint describing the input port.
84 $ref: video-interfaces.yaml#
85 unevaluatedProperties: false
86 description: Endpoint connected to input device
94 enum: [8, 9, 10, 11, 12, 13, 14]
100 Presence of this boolean property decides whether clock is
101 continuous or noncontinuous.
103 remote-endpoint: true
106 $ref: /schemas/graph.yaml#/$defs/port-base
107 unevaluatedProperties: false
109 Output port node, single endpoint describing the output port.
113 unevaluatedProperties: false
114 $ref: video-interfaces.yaml#
115 description: Endpoint connected to output device
123 enum: [8, 9, 10, 11, 12, 13, 14]
126 remote-endpoint: true
132 additionalProperties: false
142 # Example for connecting to a parallel sensor controller block (video pipe)
143 # and the input is received from Synopsys IDI interface
146 compatible = "microchip,sama7g5-csi2dc";
147 reg = <0xe1404000 0x500>;
148 clocks = <&pclk>, <&scck>;
149 clock-names = "pclk", "scck";
152 #address-cells = <1>;
155 reg = <0>; /* must be 0, first child port */
156 csi2dc_in: endpoint { /* input from IDI interface */
157 bus-type = <4>; /* MIPI CSI2 D-PHY */
158 remote-endpoint = <&csi2host_out>;
163 reg = <1>; /* must be 1, second child port */
164 csi2dc_out: endpoint {
165 remote-endpoint = <&xisc_in>; /* output to sensor controller */
171 # Example for connecting to a DMA master as an AHB slave
172 # and the input is received from Synopsys IDI interface
174 #include <dt-bindings/dma/at91.h>
176 compatible = "microchip,sama7g5-csi2dc";
177 reg = <0xe1404000 0x500>;
178 clocks = <&pclk>, <&scck>;
179 clock-names = "pclk", "scck";
180 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>;
184 #address-cells = <1>;
187 reg = <0>; /* must be 0, first child port */
188 csi2dc_input: endpoint { /* input from IDI interface */
189 remote-endpoint = <&csi2host_out>;