1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Video Decode Accelerator
11 - Yunfei Dong <yunfei.dong@mediatek.com>
14 Mediatek Video Decode is the video decode hardware present in Mediatek
15 SoCs which supports high resolution decoding functionalities.
20 - mediatek,mt8173-vcodec-dec
21 - mediatek,mt8183-vcodec-dec
54 assigned-clock-parents: true
56 assigned-clock-rates: true
65 List of the hardware port in respective IOMMU block for current Socs.
66 Refer to bindings/iommu/mediatek,iommu.yaml.
69 $ref: /schemas/types.yaml#/definitions/phandle
71 Describes point to vpu.
74 $ref: /schemas/types.yaml#/definitions/phandle
76 Describes point to scp.
79 $ref: /schemas/types.yaml#/definitions/phandle
80 description: Phandle to the vdecsys syscon node.
97 - mediatek,mt8183-vcodec-dec
117 - mediatek,mt8173-vcodec-dec
132 - const: clk_cci400_sel
137 - const: vdec_bus_clk_src
139 additionalProperties: false
143 #include <dt-bindings/interrupt-controller/arm-gic.h>
144 #include <dt-bindings/clock/mt8173-clk.h>
145 #include <dt-bindings/memory/mt8173-larb-port.h>
146 #include <dt-bindings/interrupt-controller/irq.h>
147 #include <dt-bindings/power/mt8173-power.h>
149 vcodec_dec: vcodec@16020000 {
150 compatible = "mediatek,mt8173-vcodec-dec";
151 reg = <0x16020000 0x1000>, /*VDEC_MISC*/
152 <0x16021000 0x800>, /*VDEC_LD*/
153 <0x16021800 0x800>, /*VDEC_TOP*/
154 <0x16022000 0x1000>, /*VDEC_CM*/
155 <0x16023000 0x1000>, /*VDEC_AD*/
156 <0x16024000 0x1000>, /*VDEC_AV*/
157 <0x16025000 0x1000>, /*VDEC_PP*/
158 <0x16026800 0x800>, /*VP8_VD*/
159 <0x16027000 0x800>, /*VP6_VD*/
160 <0x16027800 0x800>, /*VP8_VL*/
161 <0x16028400 0x400>; /*VP9_VD*/
162 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
163 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
164 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
165 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
166 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
167 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
168 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
169 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
170 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
171 mediatek,vpu = <&vpu>;
172 mediatek,vdecsys = <&vdecsys>;
173 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
174 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
175 <&topckgen CLK_TOP_UNIVPLL_D2>,
176 <&topckgen CLK_TOP_CCI400_SEL>,
177 <&topckgen CLK_TOP_VDEC_SEL>,
178 <&topckgen CLK_TOP_VCODECPLL>,
179 <&apmixedsys CLK_APMIXED_VENCPLL>,
180 <&topckgen CLK_TOP_VENC_LT_SEL>,
181 <&topckgen CLK_TOP_VCODECPLL_370P5>;
182 clock-names = "vcodecpll",
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191 <&topckgen CLK_TOP_CCI400_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
193 <&apmixedsys CLK_APMIXED_VCODECPLL>,
194 <&apmixedsys CLK_APMIXED_VENCPLL>;
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
196 <&topckgen CLK_TOP_UNIVPLL_D2>,
197 <&topckgen CLK_TOP_VCODECPLL>;
198 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;