1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Video Decode Accelerator
11 - Yunfei Dong <yunfei.dong@mediatek.com>
14 Mediatek Video Decode is the video decode hardware present in Mediatek
15 SoCs which supports high resolution decoding functionalities.
20 - mediatek,mt8173-vcodec-dec
21 - mediatek,mt8183-vcodec-dec
36 - const: clk_cci400_sel
41 - const: vdec_bus_clk_src
45 assigned-clock-parents: true
47 assigned-clock-rates: true
56 List of the hardware port in respective IOMMU block for current Socs.
57 Refer to bindings/iommu/mediatek,iommu.yaml.
62 Describes the physical address space of IOMMU maps to memory.
65 $ref: /schemas/types.yaml#/definitions/phandle
67 Describes point to vpu.
70 $ref: /schemas/types.yaml#/definitions/phandle
72 Describes point to scp.
82 - assigned-clock-parents
90 - mediatek,mt8183-vcodec-dec
101 - mediatek,mt8173-vcodec-dec
107 additionalProperties: false
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 #include <dt-bindings/clock/mt8173-clk.h>
113 #include <dt-bindings/memory/mt8173-larb-port.h>
114 #include <dt-bindings/interrupt-controller/irq.h>
115 #include <dt-bindings/power/mt8173-power.h>
117 vcodec_dec: vcodec@16000000 {
118 compatible = "mediatek,mt8173-vcodec-dec";
119 reg = <0x16000000 0x100>, /*VDEC_SYS*/
120 <0x16020000 0x1000>, /*VDEC_MISC*/
121 <0x16021000 0x800>, /*VDEC_LD*/
122 <0x16021800 0x800>, /*VDEC_TOP*/
123 <0x16022000 0x1000>, /*VDEC_CM*/
124 <0x16023000 0x1000>, /*VDEC_AD*/
125 <0x16024000 0x1000>, /*VDEC_AV*/
126 <0x16025000 0x1000>, /*VDEC_PP*/
127 <0x16026800 0x800>, /*VP8_VD*/
128 <0x16027000 0x800>, /*VP6_VD*/
129 <0x16027800 0x800>, /*VP8_VL*/
130 <0x16028400 0x400>; /*VP9_VD*/
131 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
132 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
133 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
134 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
135 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
136 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
137 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
138 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
139 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
140 mediatek,vpu = <&vpu>;
141 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
142 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
143 <&topckgen CLK_TOP_UNIVPLL_D2>,
144 <&topckgen CLK_TOP_CCI400_SEL>,
145 <&topckgen CLK_TOP_VDEC_SEL>,
146 <&topckgen CLK_TOP_VCODECPLL>,
147 <&apmixedsys CLK_APMIXED_VENCPLL>,
148 <&topckgen CLK_TOP_VENC_LT_SEL>,
149 <&topckgen CLK_TOP_VCODECPLL_370P5>;
150 clock-names = "vcodecpll",
158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
159 <&topckgen CLK_TOP_CCI400_SEL>,
160 <&topckgen CLK_TOP_VDEC_SEL>,
161 <&apmixedsys CLK_APMIXED_VCODECPLL>,
162 <&apmixedsys CLK_APMIXED_VENCPLL>;
163 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
164 <&topckgen CLK_TOP_UNIVPLL_D2>,
165 <&topckgen CLK_TOP_VCODECPLL>;
166 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;