1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek JPEG Encoder
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
13 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
17 const: mediatek,mt8195-jpgenc
25 Points to the respective IOMMU block with master port as argument, see
26 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
27 Ports are according to the HW.
37 # Required child node:
42 The jpeg encoder hardware device node which should be added as subnodes to
47 const: mediatek,mt8195-jpgenc-hw
56 List of the hardware port in respective IOMMU block for current Socs.
57 Refer to bindings/iommu/mediatek,iommu.yaml.
81 additionalProperties: false
89 additionalProperties: false
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/memory/mt8195-memory-port.h>
95 #include <dt-bindings/interrupt-controller/irq.h>
96 #include <dt-bindings/clock/mt8195-clk.h>
97 #include <dt-bindings/power/mt8195-power.h>
100 #address-cells = <2>;
104 compatible = "mediatek,mt8195-jpgenc";
105 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
106 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
107 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
108 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
109 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
110 #address-cells = <2>;
115 compatible = "mediatek,mt8195-jpgenc-hw";
116 reg = <0 0x1a030000 0 0x10000>;
117 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
118 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
119 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
120 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
121 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
122 clocks = <&vencsys CLK_VENC_JPGENC>;
123 clock-names = "jpgenc";
124 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
128 compatible = "mediatek,mt8195-jpgenc-hw";
129 reg = <0 0x1b030000 0 0x10000>;
130 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
131 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
132 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
133 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
134 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
135 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
136 clock-names = "jpgenc";
137 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;