Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek Write DMA with Rotation
   8
   9 maintainers:
  10   - Matthias Brugger <matthias.bgg@gmail.com>
  11   - Moudy Ho <moudy.ho@mediatek.com>
  12
  13 description: |
  14   One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
  15
  16 properties:
  17   compatible:
  18     items:
  19       - enum:
  20           - mediatek,mt8183-mdp3-wrot
  21
  22   reg:
  23     maxItems: 1
  24
  25   mediatek,gce-client-reg:
  26     $ref: /schemas/types.yaml#/definitions/phandle-array
  27     items:
  28       items:
  29         - description: phandle of GCE
  30         - description: GCE subsys id
  31         - description: register offset
  32         - description: register size
  33     description: The register of client driver can be configured by gce with
  34       4 arguments defined in this property. Each GCE subsys id is mapping to
  35       a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
  36
  37   mediatek,gce-events:
  38     description:
  39       The event id which is mapping to the specific hardware event signal
  40       to gce. The event id is defined in the gce header
  41       include/dt-bindings/gce/<chip>-gce.h of each chips.
  42     $ref: /schemas/types.yaml#/definitions/uint32-array
  43
  44   power-domains:
  45     maxItems: 1
  46
  47   clocks:
  48     minItems: 1
  49
  50   iommus:
  51     maxItems: 1
  52
  53   '#dma-cells':
  54     const: 1
  55
  56 required:
  57   - compatible
  58   - reg
  59   - mediatek,gce-client-reg
  60   - mediatek,gce-events
  61   - power-domains
  62   - clocks
  63   - iommus
  64   - '#dma-cells'
  65
  66 additionalProperties: false
  67
  68 examples:
  69   - |
  70     #include <dt-bindings/clock/mt8183-clk.h>
  71     #include <dt-bindings/gce/mt8183-gce.h>
  72     #include <dt-bindings/power/mt8183-power.h>
  73     #include <dt-bindings/memory/mt8183-larb-port.h>
  74
  75     dma-controller@14005000 {
  76         compatible = "mediatek,mt8183-mdp3-wrot";
  77         reg = <0x14005000 0x1000>;
  78         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
  79         mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
  80                               <CMDQ_EVENT_MDP_WROT0_EOF>;
  81         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
  82         clocks = <&mmsys CLK_MM_MDP_WROT0>;
  83         iommus = <&iommu>;
  84         #dma-cells = <1>;
  85     };