1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Read Direct Memory Access
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
14 MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
15 It contains one line buffer to store the sufficient pixel data, and
16 must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24 - const: mediatek,mt8183-mdp3-rdma
29 mediatek,gce-client-reg:
30 $ref: /schemas/types.yaml#/definitions/phandle-array
33 - description: phandle of GCE
34 - description: GCE subsys id
35 - description: register offset
36 - description: register size
37 description: The register of client driver can be configured by gce with
38 4 arguments defined in this property. Each GCE subsys id is mapping to
39 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
43 The event id which is mapping to the specific hardware event signal
44 to gce. The event id is defined in the gce header
45 include/dt-bindings/gce/<chip>-gce.h of each chips.
46 $ref: /schemas/types.yaml#/definitions/uint32-array
53 - description: RDMA clock
54 - description: RSZ clock
61 - description: used for 1st data pipe from RDMA
62 - description: used for 2nd data pipe from RDMA
67 - mediatek,gce-client-reg
74 additionalProperties: false
78 #include <dt-bindings/clock/mt8183-clk.h>
79 #include <dt-bindings/gce/mt8183-gce.h>
80 #include <dt-bindings/power/mt8183-power.h>
81 #include <dt-bindings/memory/mt8183-larb-port.h>
83 mdp3_rdma0: mdp3-rdma0@14001000 {
84 compatible = "mediatek,mt8183-mdp3-rdma";
85 reg = <0x14001000 0x1000>;
86 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
87 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
88 <CMDQ_EVENT_MDP_RDMA0_EOF>;
89 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
90 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
91 <&mmsys CLK_MM_MDP_RSZ1>;
93 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
94 <&gce 21 CMDQ_THR_PRIO_LOWEST>;