1 Cadence MIPI-CSI2 TX controller
2 ===============================
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
5 4 CSI lanes in output, and up to 4 different pixel streams in input.
8 - compatible: must be set to "cdns,csi2tx"
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
12 * esc_clk: escape mode clock
13 * p_clk: register bank clock
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
15 implemented in hardware, between 0 and 3
18 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
19 - phy-names: must contain "dphy"
22 - ports: A ports node with one port child node per device input and output
23 port, in accordance with the video interface bindings defined in
24 Documentation/devicetree/bindings/media/video-interfaces.txt. The
25 port nodes are numbered as follows.
28 -----------------------------
35 The stream input port nodes are optional if they are not
36 connected to anything at the hardware level or implemented
37 in the design. Since there is only one endpoint per port,
38 the endpoints are not numbered.
42 csi2tx: csi-bridge@0d0e1000 {
43 compatible = "cdns,csi2tx";
44 reg = <0x0d0e1000 0x1000>;
45 clocks = <&byteclock>, <&byteclock>,
46 <&coreclock>, <&coreclock>,
47 <&coreclock>, <&coreclock>;
48 clock-names = "p_clk", "esc_clk",
49 "pixel_if0_clk", "pixel_if1_clk",
50 "pixel_if2_clk", "pixel_if3_clk";
59 csi2tx_out: endpoint {
60 remote-endpoint = <&remote_in>;
69 csi2tx_in_stream0: endpoint {
70 remote-endpoint = <&stream0_out>;
77 csi2tx_in_stream1: endpoint {
78 remote-endpoint = <&stream1_out>;
85 csi2tx_in_stream2: endpoint {
86 remote-endpoint = <&stream2_out>;
93 csi2tx_in_stream3: endpoint {
94 remote-endpoint = <&stream3_out>;