Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Allwinner A31 CMOS Sensor Interface (CSI)
   8
   9 maintainers:
  10   - Chen-Yu Tsai <wens@csie.org>
  11   - Maxime Ripard <mripard@kernel.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - allwinner,sun6i-a31-csi
  17       - allwinner,sun8i-a83t-csi
  18       - allwinner,sun8i-h3-csi
  19       - allwinner,sun8i-v3s-csi
  20       - allwinner,sun50i-a64-csi
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   clocks:
  29     items:
  30       - description: Bus Clock
  31       - description: Module Clock
  32       - description: DRAM Clock
  33
  34   clock-names:
  35     items:
  36       - const: bus
  37       - const: mod
  38       - const: ram
  39
  40   resets:
  41     maxItems: 1
  42
  43   port:
  44     $ref: /schemas/graph.yaml#/$defs/port-base
  45     description: Parallel input port, connect to a parallel sensor
  46
  47     properties:
  48       endpoint:
  49         $ref: video-interfaces.yaml#
  50         unevaluatedProperties: false
  51
  52         properties:
  53           bus-width:
  54             enum: [ 8, 10, 12, 16 ]
  55
  56           pclk-sample: true
  57           hsync-active: true
  58           vsync-active: true
  59
  60         required:
  61           - bus-width
  62
  63     unevaluatedProperties: false
  64
  65   ports:
  66     $ref: /schemas/graph.yaml#/properties/ports
  67
  68     properties:
  69       port@0:
  70         $ref: "#/properties/port"
  71
  72       port@1:
  73         $ref: /schemas/graph.yaml#/properties/port
  74         description: MIPI CSI-2 bridge input port
  75
  76       port@2:
  77         $ref: /schemas/graph.yaml#/properties/port
  78         description: Internal output port to the ISP
  79
  80     anyOf:
  81       - required:
  82           - port@0
  83       - required:
  84           - port@1
  85
  86 required:
  87   - compatible
  88   - reg
  89   - interrupts
  90   - clocks
  91   - clock-names
  92   - resets
  93
  94 oneOf:
  95   - required:
  96       - ports
  97   - required:
  98       - port
  99
 100 additionalProperties: false
 101
 102 examples:
 103   - |
 104     #include <dt-bindings/interrupt-controller/arm-gic.h>
 105     #include <dt-bindings/clock/sun8i-v3s-ccu.h>
 106     #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 107
 108     csi1: csi@1cb4000 {
 109         compatible = "allwinner,sun8i-v3s-csi";
 110         reg = <0x01cb4000 0x1000>;
 111         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 112         clocks = <&ccu CLK_BUS_CSI>,
 113                  <&ccu CLK_CSI1_SCLK>,
 114                  <&ccu CLK_DRAM_CSI>;
 115         clock-names = "bus",
 116                       "mod",
 117                       "ram";
 118         resets = <&ccu RST_BUS_CSI>;
 119
 120         ports {
 121             #address-cells = <1>;
 122             #size-cells = <0>;
 123
 124             port@0 {
 125                 reg = <0>;
 126                 /* Parallel bus endpoint */
 127                 csi1_ep: endpoint {
 128                     remote-endpoint = <&adv7611_ep>;
 129                     bus-width = <16>;
 130
 131                     /*
 132                      * If hsync-active/vsync-active are missing,
 133                      * embedded BT.656 sync is used.
 134                      */
 135                     hsync-active = <0>; /* Active low */
 136                     vsync-active = <0>; /* Active low */
 137                     pclk-sample = <1>;  /* Rising */
 138                 };
 139             };
 140         };
 141     };
 142
 143 ...