1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/allegro,al5e.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs Device Tree Bindings
10 - Michael Tretter <m.tretter@pengutronix.de>
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
16 Each actual codec engine is controlled by a microcontroller (MCU). Host
17 software uses a provided mailbox interface to communicate with the MCU. The
18 MCUs share an interrupt.
24 - const: allegro,al5e-1.1
27 - const: allegro,al5d-1.1
32 - description: The registers
33 - description: The SRAM
45 - description: Core clock
46 - description: MCU clock
47 - description: Core AXI master port clock
48 - description: MCU AXI master port clock
49 - description: AXI4-Lite slave port clock
55 - const: m_axi_core_aclk
56 - const: m_axi_mcu_aclk
57 - const: s_axi_lite_aclk
67 additionalProperties: False
75 al5e: video-codec@a0009000 {
76 compatible = "allegro,al5e-1.1", "allegro,al5e";
77 reg = <0 0xa0009000 0 0x1000>,
78 <0 0xa0000000 0 0x8000>;
79 reg-names = "regs", "sram";
80 interrupts = <0 96 4>;
81 clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
82 <&clkc 71>, <&clkc 71>, <&clkc 71>;
83 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
84 "m_axi_mcu_aclk", "s_axi_lite_aclk";
92 al5d: video-codec@a0029000 {
93 compatible = "allegro,al5d-1.1", "allegro,al5d";
94 reg = <0 0xa0029000 0 0x1000>,
95 <0 0xa0020000 0 0x8000>;
96 reg-names = "regs", "sram";
97 interrupts = <0 96 4>;
98 clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
99 <&clkc 71>, <&clkc 71>, <&clkc 71>;
100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
101 "m_axi_mcu_aclk", "s_axi_lite_aclk";