1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
15 addressing scheme called protocol, client and signal. For example, consider an
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
17 Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
18 a case, the client would be Modem (client-id is 2) and the signal would be
19 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
21 for the list of such IDs.
46 interrupt-controller: true
51 The first cell is the client-id, the second cell is the signal-id and the
52 third cell is the interrupt type.
57 The first cell is the client-id, and the second cell is the signal-id.
63 - interrupt-controller
67 additionalProperties: false
71 #include <dt-bindings/interrupt-controller/arm-gic.h>
72 #include <dt-bindings/mailbox/qcom-ipcc.h>
75 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
76 reg = <0x408000 0x1000>;
77 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
79 #interrupt-cells = <3>;