1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM MHU Mailbox Controller
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
14 independent channels/links to communicate with remote processor(s). MHU links
15 are hardwired on a platform. A link raises interrupt for any received data.
16 However, there is no specified way of knowing if the sent data has been read
17 by the remote. This driver assumes the sender polls STAT register and the
18 remote clears it after having read the data. The last channel is specified to
19 be a 'Secure' resource, hence can't be used by Linux running NS.
21 The MHU hardware also allows operations in doorbell mode. The MHU drives the
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
23 together. It provides a set of registers to enable software to set, clear and
24 check the status of each of the bits of this register independently. The use
25 of 32 bits per interrupt line enables software to provide more information
26 about the source of the interrupt. For example, each bit of the register can
27 be associated with a type of event that can contribute to raising the
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
31 # We need a select here so we don't match all nodes with 'arm,primecell'
45 - description: Data transfer mode
48 - const: arm,primecell
50 - description: Doorbell mode
52 - const: arm,mhu-doorbell
53 - const: arm,primecell
61 - description: low-priority non-secure
62 - description: high-priority non-secure
74 Set to 1 in data transfer mode and represents index of the channel.
75 Set to 2 in doorbell mode and represents index of the channel and doorbell
85 additionalProperties: false
94 mhuA: mailbox@2b1f0000 {
96 compatible = "arm,mhu", "arm,primecell";
97 reg = <0 0x2b1f0000 0 0x1000>;
98 interrupts = <0 36 4>, /* LP-NonSecure */
99 <0 35 4>, /* HP-NonSecure */
100 <0 37 4>; /* Secure */
101 clocks = <&clock 0 2 1>;
102 clock-names = "apb_pclk";
108 compatible = "arm,scpi";
109 mboxes = <&mhuA 1>; /* HP-NonSecure */
110 shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
112 scpi_devpd: power-controller {
113 compatible = "arm,scpi-power-domains";
115 #power-domain-cells = <1>;
123 #address-cells = <2>;
126 mhuB: mailbox@2b2f0000 {
128 compatible = "arm,mhu-doorbell", "arm,primecell";
129 reg = <0 0x2b2f0000 0 0x1000>;
130 interrupts = <0 36 4>, /* LP-NonSecure */
131 <0 35 4>, /* HP-NonSecure */
132 <0 37 4>; /* Secure */
133 clocks = <&clock 0 2 1>;
134 clock-names = "apb_pclk";
140 compatible = "arm,scmi";
141 mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
142 <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
143 mbox-names = "tx", "rx";
144 shmem = <&cpu_scp_lpri0>,
147 #address-cells = <1>;
150 scmi_devpd: protocol@11 {
152 #power-domain-cells = <1>;
155 scmi_dvfs: protocol@13 {
159 mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
160 <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
161 mbox-names = "tx", "rx";
162 shmem = <&cpu_scp_hpri0>,