1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED BMC KCS Devices
10 - Andrew Jeffery <andrew@aj.id.au>
13 The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
14 interfaces on the LPC bus for in-band IPMI communication with their host.
19 - description: Channel ID derived from reg
22 - aspeed,ast2400-kcs-bmc-v2
23 - aspeed,ast2500-kcs-bmc-v2
24 - aspeed,ast2600-kcs-bmc
26 - description: Old-style with explicit channel ID, no reg
30 - aspeed,ast2400-kcs-bmc
31 - aspeed,ast2500-kcs-bmc
39 - description: IDR register
40 - description: ODR register
41 - description: STR register
44 $ref: '/schemas/types.yaml#/definitions/uint32-array'
48 The host CPU LPC IO data and status addresses for the device. For most
49 channels the status address is derived from the data address, but the
50 status address may be optionally provided.
52 aspeed,lpc-interrupts:
53 $ref: "/schemas/types.yaml#/definitions/uint32-array"
57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
58 level/sense encoding (specified in the standard fashion).
60 Note that the generated interrupt is issued from the BMC to the host, and
61 thus the target interrupt controller is not captured by the BMC's
66 $ref: '/schemas/types.yaml#/definitions/uint32'
67 description: The LPC channel number in the controller
71 $ref: '/schemas/types.yaml#/definitions/uint32'
72 description: The host CPU IO map address
78 additionalProperties: false
86 - aspeed,ast2400-kcs-bmc
87 - aspeed,ast2500-kcs-bmc
99 #include <dt-bindings/interrupt-controller/irq.h>
101 compatible = "aspeed,ast2600-kcs-bmc";
102 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
103 aspeed,lpc-io-reg = <0xca2>;
104 aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;