1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
14 its master device. Each slave device is bound to a single master device and
15 shares its clocks, power domain and irq.
17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings.
24 - rockchip,rk3568-iommu
28 - description: configuration registers for MMU instance 0
29 - description: configuration registers for MMU instance 1
34 - description: interruption for MMU instance 0
35 - description: interruption for MMU instance 1
40 - description: Core clock
41 - description: Interface clock
54 rockchip,disable-mmu-reset:
55 $ref: /schemas/types.yaml#/definitions/flag
57 Do not use the mmu reset operation.
58 Some mmu instances may produce unexpected results
59 when the reset operation is used.
69 additionalProperties: false
73 #include <dt-bindings/clock/rk3399-cru.h>
74 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 vopl_mmu: iommu@ff940300 {
77 compatible = "rockchip,iommu";
78 reg = <0xff940300 0x100>;
79 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
81 clock-names = "aclk", "iface";