1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
14 this M4U have two generations of HW architecture. Generation one uses flat
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
18 About the M4U Hardware Block Diagram, please check below:
20 EMI (External Memory Interface)
22 m4u (Multimedia Memory Management Unit)
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
30 | | Some SoCs may have GALS.
33 SMI Common(Smart Multimedia Interface Common)
35 +----------------+-------
37 | gals-rx There may be GALS in some larbs.
42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
46 +-----+-----+ +----+----+
48 | | |... | | | ... There are different ports in each larb.
50 OVL0 RDMA0 WDMA0 MC PP VLD
52 As above, The Multimedia HW will go through SMI and M4U while it
53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
54 smi local arbiter and smi common. It will control whether the Multimedia
55 HW should go though the m4u for translation or bypass it and talk
56 directly with EMI. And also SMI help control the power domain and clocks for
59 Normally we specify a local arbiter(larb) for each multimedia HW
60 like display, video decode, and camera. And there are different ports
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
62 video decode local arbiter, all these ports are according to the video HW.
64 In some SoCs, there may be a GALS(Global Async Local Sync) module between
65 smi-common and m4u, and additional GALS module between smi-larb and
66 smi-common. GALS can been seen as a "asynchronous fifo" which could help
67 synchronize for the modules in different clock frequency.
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt8167-m4u # generation two
78 - mediatek,mt8173-m4u # generation two
79 - mediatek,mt8183-m4u # generation two
80 - mediatek,mt8186-iommu-mm # generation two
81 - mediatek,mt8188-iommu-vdo # generation two
82 - mediatek,mt8188-iommu-vpp # generation two
83 - mediatek,mt8188-iommu-infra # generation two
84 - mediatek,mt8192-m4u # generation two
85 - mediatek,mt8195-iommu-vdo # generation two
86 - mediatek,mt8195-iommu-vpp # generation two
87 - mediatek,mt8195-iommu-infra # generation two
88 - mediatek,mt8365-m4u # generation two
90 - description: mt7623 generation one
92 - const: mediatek,mt7623-m4u
93 - const: mediatek,mt2701-m4u
103 - description: bclk is the block clock.
110 $ref: /schemas/types.yaml#/definitions/phandle
111 description: The phandle to the mediatek infracfg syscon
114 $ref: /schemas/types.yaml#/definitions/phandle-array
120 List of phandle to the local arbiters in the current Socs.
121 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
122 according to the local arbiter index, like larb0, larb1, larb2...
127 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
129 dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188,
130 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
131 dt-binding/memory/mt2712-larb-port.h for mt2712,
132 dt-binding/memory/mt6779-larb-port.h for mt6779,
133 dt-binding/memory/mt6795-larb-port.h for mt6795,
134 dt-binding/memory/mt8167-larb-port.h for mt8167,
135 dt-binding/memory/mt8173-larb-port.h for mt8173,
136 dt-binding/memory/mt8183-larb-port.h for mt8183,
137 dt-binding/memory/mt8186-memory-port.h for mt8186,
138 dt-binding/memory/mt8192-larb-port.h for mt8192.
139 dt-binding/memory/mt8195-memory-port.h for mt8195.
140 dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365.
157 - mediatek,mt2701-m4u
158 - mediatek,mt2712-m4u
159 - mediatek,mt6795-m4u
160 - mediatek,mt8173-m4u
161 - mediatek,mt8186-iommu-mm
162 - mediatek,mt8188-iommu-vdo
163 - mediatek,mt8188-iommu-vpp
164 - mediatek,mt8192-m4u
165 - mediatek,mt8195-iommu-vdo
166 - mediatek,mt8195-iommu-vpp
176 - mediatek,mt8186-iommu-mm
177 - mediatek,mt8188-iommu-vdo
178 - mediatek,mt8188-iommu-vpp
179 - mediatek,mt8192-m4u
180 - mediatek,mt8195-iommu-vdo
181 - mediatek,mt8195-iommu-vpp
192 - mediatek,mt2712-m4u
193 - mediatek,mt6795-m4u
194 - mediatek,mt8173-m4u
200 - if: # The IOMMUs don't have larbs.
206 - mediatek,mt8188-iommu-infra
207 - mediatek,mt8195-iommu-infra
213 additionalProperties: false
217 #include <dt-bindings/clock/mt8173-clk.h>
218 #include <dt-bindings/interrupt-controller/arm-gic.h>
220 iommu: iommu@10205000 {
221 compatible = "mediatek,mt8173-m4u";
222 reg = <0x10205000 0x1000>;
223 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
224 clocks = <&infracfg CLK_INFRA_M4U>;
225 clock-names = "bclk";
226 mediatek,infracfg = <&infracfg>;
227 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
228 <&larb3>, <&larb4>, <&larb5>;