1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek IOMMU Architecture Implementation
10 - Yong Wu <yong.wu@mediatek.com>
13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
14 this M4U have two generations of HW architecture. Generation one uses flat
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
18 About the M4U Hardware Block Diagram, please check below:
20 EMI (External Memory Interface)
22 m4u (Multimedia Memory Management Unit)
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
30 | | Some SoCs may have GALS.
33 SMI Common(Smart Multimedia Interface Common)
35 +----------------+-------
37 | gals-rx There may be GALS in some larbs.
42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
46 +-----+-----+ +----+----+
48 | | |... | | | ... There are different ports in each larb.
50 OVL0 RDMA0 WDMA0 MC PP VLD
52 As above, The Multimedia HW will go through SMI and M4U while it
53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
54 smi local arbiter and smi common. It will control whether the Multimedia
55 HW should go though the m4u for translation or bypass it and talk
56 directly with EMI. And also SMI help control the power domain and clocks for
59 Normally we specify a local arbiter(larb) for each multimedia HW
60 like display, video decode, and camera. And there are different ports
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
62 video decode local arbiter, all these ports are according to the video HW.
64 In some SoCs, there may be a GALS(Global Async Local Sync) module between
65 smi-common and m4u, and additional GALS module between smi-larb and
66 smi-common. GALS can been seen as a "asynchronous fifo" which could help
67 synchronize for the modules in different clock frequency.
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt8167-m4u # generation two
77 - mediatek,mt8173-m4u # generation two
78 - mediatek,mt8183-m4u # generation two
79 - mediatek,mt8192-m4u # generation two
81 - description: mt7623 generation one
83 - const: mediatek,mt7623-m4u
84 - const: mediatek,mt2701-m4u
94 - description: bclk is the block clock.
101 $ref: /schemas/types.yaml#/definitions/phandle-array
105 List of phandle to the local arbiters in the current Socs.
106 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
107 according to the local arbiter index, like larb0, larb1, larb2...
112 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
114 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
115 dt-binding/memory/mt2712-larb-port.h for mt2712,
116 dt-binding/memory/mt6779-larb-port.h for mt6779,
117 dt-binding/memory/mt8167-larb-port.h for mt8167,
118 dt-binding/memory/mt8173-larb-port.h for mt8173,
119 dt-binding/memory/mt8183-larb-port.h for mt8183,
120 dt-binding/memory/mt8192-larb-port.h for mt8192.
138 - mediatek,mt2701-m4u
139 - mediatek,mt2712-m4u
140 - mediatek,mt8173-m4u
141 - mediatek,mt8192-m4u
151 - mediatek,mt8192-m4u
157 additionalProperties: false
161 #include <dt-bindings/clock/mt8173-clk.h>
162 #include <dt-bindings/interrupt-controller/arm-gic.h>
164 iommu: iommu@10205000 {
165 compatible = "mediatek,mt8173-m4u";
166 reg = <0x10205000 0x1000>;
167 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
168 clocks = <&infracfg CLK_INFRA_M4U>;
169 clock-names = "bclk";
170 mediatek,larbs = <&larb0 &larb1 &larb2
171 &larb3 &larb4 &larb5>;
176 #include <dt-bindings/memory/mt8173-larb-port.h>
178 /* Example for a client device */
180 compatible = "mediatek,mt8173-disp";
181 iommus = <&iommu M4U_PORT_DISP_OVL0>,
182 <&iommu M4U_PORT_DISP_RDMA0>;