1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
33 - description: Qcom SoCs implementing "arm,mmu-500"
36 - qcom,qcm2290-smmu-500
37 - qcom,sc7180-smmu-500
38 - qcom,sc7280-smmu-500
39 - qcom,sc8180x-smmu-500
40 - qcom,sc8280xp-smmu-500
41 - qcom,sdm845-smmu-500
44 - qcom,sm6350-smmu-500
45 - qcom,sm6375-smmu-500
46 - qcom,sm8150-smmu-500
47 - qcom,sm8250-smmu-500
48 - qcom,sm8350-smmu-500
49 - qcom,sm8450-smmu-500
51 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
56 - const: qcom,adreno-smmu
58 - description: Marvell SoCs implementing "arm,mmu-500"
60 - const: marvell,ap806-smmu-500
62 - description: NVIDIA SoCs that require memory controller interaction
63 and may program multiple ARM MMU-500s identically with the memory
64 controller interleaving translations between multiple instances
65 for improved performance.
68 - nvidia,tegra186-smmu
69 - nvidia,tegra194-smmu
70 - nvidia,tegra234-smmu
71 - const: nvidia,smmu-500
93 description: The number of global interrupts exposed by the device.
94 $ref: /schemas/types.yaml#/definitions/uint32
96 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
101 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
102 value of 1, each IOMMU specifier represents a distinct stream ID emitted
103 by that device into the relevant SMMU.
105 SMMUs with stream matching support and complex masters may use a value of
106 2, where the second cell of the IOMMU specifier represents an SMR mask to
107 combine with the ID in the first cell. Care must be taken to ensure the
108 set of matched IDs does not result in conflicts.
112 maxItems: 388 # 260 plus 128 contexts
114 Interrupt list, with the first #global-interrupts entries corresponding to
115 the global interrupts and any following entries corresponding to context
116 interrupts, specified in order of their indexing by the SMMU.
118 For SMMUv2 implementations, there must be exactly one interrupt per
119 context bank. In the case of a single, combined interrupt, it must be
120 listed multiple times.
124 Present if page table walks made by the SMMU are cache coherent with the
127 NOTE: this only applies to the SMMU itself, not masters connected
128 upstream of the SMMU.
130 calxeda,smmu-secure-config-access:
133 Enable proper handling of buggy implementations that always use secure
134 access to SMMU configuration registers. In this case non-secure aliases of
135 secure registers have to be used during SMMU configuration.
138 $ref: /schemas/types.yaml#/definitions/uint32
140 For SMMUs supporting stream matching and using #iommu-cells = <1>,
141 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
142 be programmed into the SMRn.MASK field of every stream match register
143 used). For cases where it is desirable to ignore some portion of every
144 Stream ID (e.g. for certain MMU-500 configurations given globally unique
145 input IDs). This property is not valid for SMMUs using stream indexing, or
146 using stream matching with #iommu-cells = <2>, and may be ignored if
147 present in such cases.
156 - description: bus clock required for downstream bus access and for the
158 - description: interface clock required to access smmu's registers
159 through the TCU's programming interface.
164 nvidia,memory-controller:
166 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
167 The memory controller needs to be programmed with a mapping of memory
168 client IDs to ARM SMMU stream IDs.
170 If this property is absent, the mapping programmed by early firmware
171 will be used and it is not guaranteed that IOMMU translations will be
172 enabled for any given device.
173 $ref: /schemas/types.yaml#/definitions/phandle
178 - '#global-interrupts'
182 additionalProperties: false
190 - nvidia,tegra186-smmu
191 - nvidia,tegra194-smmu
192 - nvidia,tegra234-smmu
199 # The reference to the memory controller is required to ensure that the
200 # memory client to stream ID mapping can be done synchronously with the
203 - nvidia,memory-controller
211 /* SMMU with stream matching or stream indexing */
212 smmu1: iommu@ba5e0000 {
213 compatible = "arm,smmu-v1";
214 reg = <0xba5e0000 0x10000>;
215 #global-interrupts = <2>;
216 interrupts = <0 32 4>,
218 <0 34 4>, /* This is the first context interrupt */
225 /* device with two stream IDs, 0 and 7 */
232 /* SMMU with stream matching */
233 smmu2: iommu@ba5f0000 {
234 compatible = "arm,smmu-v1";
235 reg = <0xba5f0000 0x10000>;
236 #global-interrupts = <2>;
237 interrupts = <0 38 4>,
239 <0 40 4>, /* This is the first context interrupt */
246 /* device with stream IDs 0 and 7 */
248 iommus = <&smmu2 0 0>,
252 /* device with stream IDs 1, 17, 33 and 49 */
254 iommus = <&smmu2 1 0x30>;
258 /* ARM MMU-500 with 10-bit stream ID input configuration */
259 smmu3: iommu@ba600000 {
260 compatible = "arm,mmu-500", "arm,smmu-v2";
261 reg = <0xba600000 0x10000>;
262 #global-interrupts = <2>;
263 interrupts = <0 44 4>,
265 <0 46 4>, /* This is the first context interrupt */
270 /* always ignore appended 5-bit TBU number */
271 stream-match-mask = <0x7c00>;
275 /* bus whose child devices emit one unique 10-bit stream
276 ID each, but may master through multiple SMMU TBUs */
277 iommu-map = <0 &smmu3 0 0x400>;
283 /* Qcom's arm,smmu-v2 implementation */
284 #include <dt-bindings/interrupt-controller/arm-gic.h>
285 #include <dt-bindings/interrupt-controller/irq.h>
286 smmu4: iommu@d00000 {
287 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
288 reg = <0xd00000 0x10000>;
290 #global-interrupts = <1>;
291 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
295 power-domains = <&mmcc 0>;
297 clocks = <&mmcc 123>,
299 clock-names = "bus", "iface";