1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
59 - qcom,sm8650-smmu-500
60 - qcom,x1e80100-smmu-500
61 - const: qcom,smmu-500
64 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 # Do not add additional SoC to this list. Instead use two previous lists.
69 - qcom,qcm2290-smmu-500
70 - qcom,sc7180-smmu-500
71 - qcom,sc7280-smmu-500
72 - qcom,sc8180x-smmu-500
73 - qcom,sc8280xp-smmu-500
74 - qcom,sdm845-smmu-500
75 - qcom,sm6115-smmu-500
76 - qcom,sm6350-smmu-500
77 - qcom,sm6375-smmu-500
78 - qcom,sm8150-smmu-500
79 - qcom,sm8250-smmu-500
80 - qcom,sm8350-smmu-500
81 - qcom,sm8450-smmu-500
83 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
86 - qcom,sa8775p-smmu-500
87 - qcom,sc7280-smmu-500
88 - qcom,sc8280xp-smmu-500
89 - qcom,sm6115-smmu-500
90 - qcom,sm6125-smmu-500
91 - qcom,sm8150-smmu-500
92 - qcom,sm8250-smmu-500
93 - qcom,sm8350-smmu-500
94 - qcom,sm8450-smmu-500
95 - qcom,sm8550-smmu-500
96 - const: qcom,adreno-smmu
97 - const: qcom,smmu-500
99 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
102 # Do not add additional SoC to this list. Instead use previous list.
104 - qcom,sc7280-smmu-500
105 - qcom,sm8150-smmu-500
106 - qcom,sm8250-smmu-500
107 - const: qcom,adreno-smmu
109 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
112 - qcom,msm8996-smmu-v2
113 - qcom,sc7180-smmu-v2
114 - qcom,sdm630-smmu-v2
115 - qcom,sdm845-smmu-v2
116 - qcom,sm6350-smmu-v2
117 - qcom,sm7150-smmu-v2
118 - const: qcom,adreno-smmu
119 - const: qcom,smmu-v2
120 - description: Qcom Adreno GPUs on Google Cheza platform
122 - const: qcom,sdm845-smmu-v2
123 - const: qcom,smmu-v2
124 - description: Marvell SoCs implementing "arm,mmu-500"
126 - const: marvell,ap806-smmu-500
128 - description: NVIDIA SoCs that require memory controller interaction
129 and may program multiple ARM MMU-500s identically with the memory
130 controller interleaving translations between multiple instances
131 for improved performance.
134 - nvidia,tegra186-smmu
135 - nvidia,tegra194-smmu
136 - nvidia,tegra234-smmu
137 - const: nvidia,smmu-500
158 '#global-interrupts':
159 description: The number of global interrupts exposed by the device.
160 $ref: /schemas/types.yaml#/definitions/uint32
162 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
167 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
168 value of 1, each IOMMU specifier represents a distinct stream ID emitted
169 by that device into the relevant SMMU.
171 SMMUs with stream matching support and complex masters may use a value of
172 2, where the second cell of the IOMMU specifier represents an SMR mask to
173 combine with the ID in the first cell. Care must be taken to ensure the
174 set of matched IDs does not result in conflicts.
178 maxItems: 388 # 260 plus 128 contexts
180 Interrupt list, with the first #global-interrupts entries corresponding to
181 the global interrupts and any following entries corresponding to context
182 interrupts, specified in order of their indexing by the SMMU.
184 For SMMUv2 implementations, there must be exactly one interrupt per
185 context bank. In the case of a single, combined interrupt, it must be
186 listed multiple times.
190 Present if page table walks made by the SMMU are cache coherent with the
193 NOTE: this only applies to the SMMU itself, not masters connected
194 upstream of the SMMU.
196 calxeda,smmu-secure-config-access:
199 Enable proper handling of buggy implementations that always use secure
200 access to SMMU configuration registers. In this case non-secure aliases of
201 secure registers have to be used during SMMU configuration.
204 $ref: /schemas/types.yaml#/definitions/uint32
206 For SMMUs supporting stream matching and using #iommu-cells = <1>,
207 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
208 be programmed into the SMRn.MASK field of every stream match register
209 used). For cases where it is desirable to ignore some portion of every
210 Stream ID (e.g. for certain MMU-500 configurations given globally unique
211 input IDs). This property is not valid for SMMUs using stream indexing, or
212 using stream matching with #iommu-cells = <2>, and may be ignored if
213 present in such cases.
227 nvidia,memory-controller:
229 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
230 The memory controller needs to be programmed with a mapping of memory
231 client IDs to ARM SMMU stream IDs.
233 If this property is absent, the mapping programmed by early firmware
234 will be used and it is not guaranteed that IOMMU translations will be
235 enabled for any given device.
236 $ref: /schemas/types.yaml#/definitions/phandle
241 - '#global-interrupts'
245 additionalProperties: false
253 - nvidia,tegra186-smmu
254 - nvidia,tegra194-smmu
255 - nvidia,tegra234-smmu
262 # The reference to the memory controller is required to ensure that the
263 # memory client to stream ID mapping can be done synchronously with the
266 - nvidia,memory-controller
277 - qcom,msm8998-smmu-v2
278 - qcom,sdm630-smmu-v2
287 - description: bus clock required for downstream bus access and for
297 - description: interface clock required to access smmu's registers
298 through the TCU's programming interface.
299 - description: bus clock required for memory access
300 - description: bus clock required for GPU memory access
309 - description: interface clock required to access mnoc's registers
310 through the TCU's programming interface.
311 - description: interface clock required to access smmu's registers
312 through the TCU's programming interface.
313 - description: bus clock required for the smmu ptw
320 - qcom,sm6375-smmu-v2
329 - description: bus clock required for downstream bus access and for
339 - description: interface clock required to access smmu's registers
340 through the TCU's programming interface.
341 - description: bus clock required for memory access
342 - description: bus clock required for GPU memory access
352 - description: interface clock required to access mnoc's registers
353 through the TCU's programming interface.
354 - description: interface clock required to access smmu's registers
355 through the TCU's programming interface.
356 - description: bus clock required for downstream bus access
357 - description: bus clock required for the smmu ptw
364 - qcom,msm8996-smmu-v2
365 - qcom,sc7180-smmu-v2
366 - qcom,sdm845-smmu-v2
376 - description: bus clock required for downstream bus access and for
378 - description: interface clock required to access smmu's registers
379 through the TCU's programming interface.
386 - qcom,sa8775p-smmu-500
387 - qcom,sc7280-smmu-500
388 - qcom,sc8280xp-smmu-500
393 - const: gcc_gpu_memnoc_gfx_clk
394 - const: gcc_gpu_snoc_dvm_gfx_clk
395 - const: gpu_cc_ahb_clk
396 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
397 - const: gpu_cc_cx_gmu_clk
398 - const: gpu_cc_hub_cx_int_clk
399 - const: gpu_cc_hub_aon_clk
403 - description: GPU memnoc_gfx clock
404 - description: GPU snoc_dvm_gfx clock
405 - description: GPU ahb clock
406 - description: GPU hlos1_vote_GPU smmu clock
407 - description: GPU cx_gmu clock
408 - description: GPU hub_cx_int clock
409 - description: GPU hub_aon clock
416 - qcom,sm6350-smmu-v2
417 - qcom,sm7150-smmu-v2
418 - qcom,sm8150-smmu-500
419 - qcom,sm8250-smmu-500
430 - description: bus clock required for AHB bus access
431 - description: bus clock required for downstream bus access and for
433 - description: interface clock required to access smmu's registers
434 through the TCU's programming interface.
441 - qcom,sm8350-smmu-500
442 - const: qcom,adreno-smmu
443 - const: qcom,smmu-500
452 - const: hlos1_vote_gpu_smmu
465 - qcom,sm6115-smmu-500
466 - qcom,sm6125-smmu-500
467 - const: qcom,adreno-smmu
468 - const: qcom,smmu-500
480 - description: GPU memory bus clock
481 - description: Voter clock required for HLOS SMMU access
482 - description: Interface clock required for register access
488 - const: qcom,sm8450-smmu-500
489 - const: qcom,adreno-smmu
490 - const: qcom,smmu-500
506 - description: GMU clock
507 - description: GPU HUB clock
508 - description: HLOS vote clock
509 - description: GPU memory bus clock
510 - description: GPU SNoC bus clock
511 - description: GPU AHB clock
517 - const: qcom,sm8550-smmu-500
518 - const: qcom,adreno-smmu
519 - const: qcom,smmu-500
532 - description: HLOS vote clock
533 - description: GPU memory bus clock
534 - description: GPU SNoC bus clock
535 - description: GPU AHB clock
537 # Disallow clocks for all other platforms with specific compatibles
544 - marvell,ap806-smmu-500
546 - qcom,qcm2290-smmu-500
547 - qcom,qdu1000-smmu-500
548 - qcom,sc7180-smmu-500
549 - qcom,sc8180x-smmu-500
550 - qcom,sdm670-smmu-500
551 - qcom,sdm845-smmu-500
552 - qcom,sdx55-smmu-500
553 - qcom,sdx65-smmu-500
554 - qcom,sm6350-smmu-500
555 - qcom,sm6375-smmu-500
556 - qcom,sm8650-smmu-500
557 - qcom,x1e80100-smmu-500
567 const: qcom,sm6375-smmu-500
572 - description: SNoC MMU TBU RT GDSC
573 - description: SNoC MMU TBU NRT GDSC
574 - description: SNoC TURING MMU TBU0 GDSC
585 /* SMMU with stream matching or stream indexing */
586 smmu1: iommu@ba5e0000 {
587 compatible = "arm,smmu-v1";
588 reg = <0xba5e0000 0x10000>;
589 #global-interrupts = <2>;
590 interrupts = <0 32 4>,
592 <0 34 4>, /* This is the first context interrupt */
599 /* device with two stream IDs, 0 and 7 */
606 /* SMMU with stream matching */
607 smmu2: iommu@ba5f0000 {
608 compatible = "arm,smmu-v1";
609 reg = <0xba5f0000 0x10000>;
610 #global-interrupts = <2>;
611 interrupts = <0 38 4>,
613 <0 40 4>, /* This is the first context interrupt */
620 /* device with stream IDs 0 and 7 */
622 iommus = <&smmu2 0 0>,
626 /* device with stream IDs 1, 17, 33 and 49 */
628 iommus = <&smmu2 1 0x30>;
632 /* ARM MMU-500 with 10-bit stream ID input configuration */
633 smmu3: iommu@ba600000 {
634 compatible = "arm,mmu-500", "arm,smmu-v2";
635 reg = <0xba600000 0x10000>;
636 #global-interrupts = <2>;
637 interrupts = <0 44 4>,
639 <0 46 4>, /* This is the first context interrupt */
644 /* always ignore appended 5-bit TBU number */
645 stream-match-mask = <0x7c00>;
649 /* bus whose child devices emit one unique 10-bit stream
650 ID each, but may master through multiple SMMU TBUs */
651 iommu-map = <0 &smmu3 0 0x400>;
657 /* Qcom's arm,smmu-v2 implementation */
658 #include <dt-bindings/interrupt-controller/arm-gic.h>
659 #include <dt-bindings/interrupt-controller/irq.h>
660 smmu4: iommu@d00000 {
661 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
662 reg = <0xd00000 0x10000>;
664 #global-interrupts = <1>;
665 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
669 power-domains = <&mmcc 0>;
671 clocks = <&mmcc 123>,
673 clock-names = "bus", "iface";