smb: client: Fix minor whitespace errors and warnings
[linux-modified.git] / Documentation / devicetree / bindings / iommu / arm,smmu.yaml
1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM System MMU Architecture Implementation
8
9 maintainers:
10   - Will Deacon <will@kernel.org>
11   - Robin Murphy <Robin.Murphy@arm.com>
12
13 description: |+
14   ARM SoCs may contain an implementation of the ARM System Memory
15   Management Unit Architecture, which can be used to provide 1 or 2 stages
16   of address translation to bus masters external to the CPU.
17
18   The SMMU may also raise interrupts in response to various fault
19   conditions.
20
21 properties:
22   $nodename:
23     pattern: "^iommu@[0-9a-f]*"
24   compatible:
25     oneOf:
26       - description: Qcom SoCs implementing "arm,smmu-v2"
27         items:
28           - enum:
29               - qcom,msm8996-smmu-v2
30               - qcom,msm8998-smmu-v2
31               - qcom,sdm630-smmu-v2
32               - qcom,sm6375-smmu-v2
33           - const: qcom,smmu-v2
34
35       - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36         items:
37           - enum:
38               - qcom,qcm2290-smmu-500
39               - qcom,qdu1000-smmu-500
40               - qcom,sa8775p-smmu-500
41               - qcom,sc7180-smmu-500
42               - qcom,sc7280-smmu-500
43               - qcom,sc8180x-smmu-500
44               - qcom,sc8280xp-smmu-500
45               - qcom,sdm670-smmu-500
46               - qcom,sdm845-smmu-500
47               - qcom,sdx55-smmu-500
48               - qcom,sdx65-smmu-500
49               - qcom,sdx75-smmu-500
50               - qcom,sm6115-smmu-500
51               - qcom,sm6125-smmu-500
52               - qcom,sm6350-smmu-500
53               - qcom,sm6375-smmu-500
54               - qcom,sm8150-smmu-500
55               - qcom,sm8250-smmu-500
56               - qcom,sm8350-smmu-500
57               - qcom,sm8450-smmu-500
58               - qcom,sm8550-smmu-500
59           - const: qcom,smmu-500
60           - const: arm,mmu-500
61
62       - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
63         deprecated: true
64         items:
65           # Do not add additional SoC to this list. Instead use two previous lists.
66           - enum:
67               - qcom,qcm2290-smmu-500
68               - qcom,sc7180-smmu-500
69               - qcom,sc7280-smmu-500
70               - qcom,sc8180x-smmu-500
71               - qcom,sc8280xp-smmu-500
72               - qcom,sdm845-smmu-500
73               - qcom,sm6115-smmu-500
74               - qcom,sm6350-smmu-500
75               - qcom,sm6375-smmu-500
76               - qcom,sm8150-smmu-500
77               - qcom,sm8250-smmu-500
78               - qcom,sm8350-smmu-500
79               - qcom,sm8450-smmu-500
80           - const: arm,mmu-500
81       - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
82         items:
83           - enum:
84               - qcom,sa8775p-smmu-500
85               - qcom,sc7280-smmu-500
86               - qcom,sc8280xp-smmu-500
87               - qcom,sm6115-smmu-500
88               - qcom,sm6125-smmu-500
89               - qcom,sm8150-smmu-500
90               - qcom,sm8250-smmu-500
91               - qcom,sm8350-smmu-500
92           - const: qcom,adreno-smmu
93           - const: qcom,smmu-500
94           - const: arm,mmu-500
95       - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
96         deprecated: true
97         items:
98           # Do not add additional SoC to this list. Instead use previous list.
99           - enum:
100               - qcom,sc7280-smmu-500
101               - qcom,sm8150-smmu-500
102               - qcom,sm8250-smmu-500
103           - const: qcom,adreno-smmu
104           - const: arm,mmu-500
105       - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
106         items:
107           - enum:
108               - qcom,msm8996-smmu-v2
109               - qcom,sc7180-smmu-v2
110               - qcom,sdm630-smmu-v2
111               - qcom,sdm845-smmu-v2
112               - qcom,sm6350-smmu-v2
113               - qcom,sm7150-smmu-v2
114           - const: qcom,adreno-smmu
115           - const: qcom,smmu-v2
116       - description: Qcom Adreno GPUs on Google Cheza platform
117         items:
118           - const: qcom,sdm845-smmu-v2
119           - const: qcom,smmu-v2
120       - description: Marvell SoCs implementing "arm,mmu-500"
121         items:
122           - const: marvell,ap806-smmu-500
123           - const: arm,mmu-500
124       - description: NVIDIA SoCs that require memory controller interaction
125           and may program multiple ARM MMU-500s identically with the memory
126           controller interleaving translations between multiple instances
127           for improved performance.
128         items:
129           - enum:
130               - nvidia,tegra186-smmu
131               - nvidia,tegra194-smmu
132               - nvidia,tegra234-smmu
133           - const: nvidia,smmu-500
134       - items:
135           - const: arm,mmu-500
136           - const: arm,smmu-v2
137       - items:
138           - enum:
139               - arm,mmu-400
140               - arm,mmu-401
141           - const: arm,smmu-v1
142       - enum:
143           - arm,smmu-v1
144           - arm,smmu-v2
145           - arm,mmu-400
146           - arm,mmu-401
147           - arm,mmu-500
148           - cavium,smmu-v2
149
150   reg:
151     minItems: 1
152     maxItems: 2
153
154   '#global-interrupts':
155     description: The number of global interrupts exposed by the device.
156     $ref: /schemas/types.yaml#/definitions/uint32
157     minimum: 0
158     maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
159
160   '#iommu-cells':
161     enum: [ 1, 2 ]
162     description: |
163       See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
164       value of 1, each IOMMU specifier represents a distinct stream ID emitted
165       by that device into the relevant SMMU.
166
167       SMMUs with stream matching support and complex masters may use a value of
168       2, where the second cell of the IOMMU specifier represents an SMR mask to
169       combine with the ID in the first cell.  Care must be taken to ensure the
170       set of matched IDs does not result in conflicts.
171
172   interrupts:
173     minItems: 1
174     maxItems: 388   # 260 plus 128 contexts
175     description: |
176       Interrupt list, with the first #global-interrupts entries corresponding to
177       the global interrupts and any following entries corresponding to context
178       interrupts, specified in order of their indexing by the SMMU.
179
180       For SMMUv2 implementations, there must be exactly one interrupt per
181       context bank. In the case of a single, combined interrupt, it must be
182       listed multiple times.
183
184   dma-coherent:
185     description: |
186       Present if page table walks made by the SMMU are cache coherent with the
187       CPU.
188
189       NOTE: this only applies to the SMMU itself, not masters connected
190       upstream of the SMMU.
191
192   calxeda,smmu-secure-config-access:
193     type: boolean
194     description:
195       Enable proper handling of buggy implementations that always use secure
196       access to SMMU configuration registers. In this case non-secure aliases of
197       secure registers have to be used during SMMU configuration.
198
199   stream-match-mask:
200     $ref: /schemas/types.yaml#/definitions/uint32
201     description: |
202       For SMMUs supporting stream matching and using #iommu-cells = <1>,
203       specifies a mask of bits to ignore when matching stream IDs (e.g. this may
204       be programmed into the SMRn.MASK field of every stream match register
205       used). For cases where it is desirable to ignore some portion of every
206       Stream ID (e.g. for certain MMU-500 configurations given globally unique
207       input IDs). This property is not valid for SMMUs using stream indexing, or
208       using stream matching with #iommu-cells = <2>, and may be ignored if
209       present in such cases.
210
211   clock-names:
212     minItems: 1
213     maxItems: 7
214
215   clocks:
216     minItems: 1
217     maxItems: 7
218
219   power-domains:
220     minItems: 1
221     maxItems: 3
222
223   nvidia,memory-controller:
224     description: |
225       A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
226       The memory controller needs to be programmed with a mapping of memory
227       client IDs to ARM SMMU stream IDs.
228
229       If this property is absent, the mapping programmed by early firmware
230       will be used and it is not guaranteed that IOMMU translations will be
231       enabled for any given device.
232     $ref: /schemas/types.yaml#/definitions/phandle
233
234 required:
235   - compatible
236   - reg
237   - '#global-interrupts'
238   - '#iommu-cells'
239   - interrupts
240
241 additionalProperties: false
242
243 allOf:
244   - if:
245       properties:
246         compatible:
247           contains:
248             enum:
249               - nvidia,tegra186-smmu
250               - nvidia,tegra194-smmu
251               - nvidia,tegra234-smmu
252     then:
253       properties:
254         reg:
255           minItems: 1
256           maxItems: 2
257
258       # The reference to the memory controller is required to ensure that the
259       # memory client to stream ID mapping can be done synchronously with the
260       # IOMMU attachment.
261       required:
262         - nvidia,memory-controller
263     else:
264       properties:
265         reg:
266           maxItems: 1
267
268   - if:
269       properties:
270         compatible:
271           contains:
272             enum:
273               - qcom,msm8998-smmu-v2
274               - qcom,sdm630-smmu-v2
275     then:
276       anyOf:
277         - properties:
278             clock-names:
279               items:
280                 - const: bus
281             clocks:
282               items:
283                 - description: bus clock required for downstream bus access and for
284                     the smmu ptw
285         - properties:
286             clock-names:
287               items:
288                 - const: iface
289                 - const: mem
290                 - const: mem_iface
291             clocks:
292               items:
293                 - description: interface clock required to access smmu's registers
294                     through the TCU's programming interface.
295                 - description: bus clock required for memory access
296                 - description: bus clock required for GPU memory access
297         - properties:
298             clock-names:
299               items:
300                 - const: iface-mm
301                 - const: iface-smmu
302                 - const: bus-smmu
303             clocks:
304               items:
305                 - description: interface clock required to access mnoc's registers
306                     through the TCU's programming interface.
307                 - description: interface clock required to access smmu's registers
308                     through the TCU's programming interface.
309                 - description: bus clock required for the smmu ptw
310
311   - if:
312       properties:
313         compatible:
314           contains:
315             enum:
316               - qcom,sm6375-smmu-v2
317     then:
318       anyOf:
319         - properties:
320             clock-names:
321               items:
322                 - const: bus
323             clocks:
324               items:
325                 - description: bus clock required for downstream bus access and for
326                     the smmu ptw
327         - properties:
328             clock-names:
329               items:
330                 - const: iface
331                 - const: mem
332                 - const: mem_iface
333             clocks:
334               items:
335                 - description: interface clock required to access smmu's registers
336                     through the TCU's programming interface.
337                 - description: bus clock required for memory access
338                 - description: bus clock required for GPU memory access
339         - properties:
340             clock-names:
341               items:
342                 - const: iface-mm
343                 - const: iface-smmu
344                 - const: bus-mm
345                 - const: bus-smmu
346             clocks:
347               items:
348                 - description: interface clock required to access mnoc's registers
349                     through the TCU's programming interface.
350                 - description: interface clock required to access smmu's registers
351                     through the TCU's programming interface.
352                 - description: bus clock required for downstream bus access
353                 - description: bus clock required for the smmu ptw
354
355   - if:
356       properties:
357         compatible:
358           contains:
359             enum:
360               - qcom,msm8996-smmu-v2
361               - qcom,sc7180-smmu-v2
362               - qcom,sdm845-smmu-v2
363     then:
364       properties:
365         clock-names:
366           items:
367             - const: bus
368             - const: iface
369
370         clocks:
371           items:
372             - description: bus clock required for downstream bus access and for
373                 the smmu ptw
374             - description: interface clock required to access smmu's registers
375                 through the TCU's programming interface.
376
377   - if:
378       properties:
379         compatible:
380           contains:
381             enum:
382               - qcom,sa8775p-smmu-500
383               - qcom,sc7280-smmu-500
384               - qcom,sc8280xp-smmu-500
385     then:
386       properties:
387         clock-names:
388           items:
389             - const: gcc_gpu_memnoc_gfx_clk
390             - const: gcc_gpu_snoc_dvm_gfx_clk
391             - const: gpu_cc_ahb_clk
392             - const: gpu_cc_hlos1_vote_gpu_smmu_clk
393             - const: gpu_cc_cx_gmu_clk
394             - const: gpu_cc_hub_cx_int_clk
395             - const: gpu_cc_hub_aon_clk
396
397         clocks:
398           items:
399             - description: GPU memnoc_gfx clock
400             - description: GPU snoc_dvm_gfx clock
401             - description: GPU ahb clock
402             - description: GPU hlos1_vote_GPU smmu clock
403             - description: GPU cx_gmu clock
404             - description: GPU hub_cx_int clock
405             - description: GPU hub_aon clock
406
407   - if:
408       properties:
409         compatible:
410           contains:
411             enum:
412               - qcom,sm6350-smmu-v2
413               - qcom,sm7150-smmu-v2
414               - qcom,sm8150-smmu-500
415               - qcom,sm8250-smmu-500
416     then:
417       properties:
418         clock-names:
419           items:
420             - const: ahb
421             - const: bus
422             - const: iface
423
424         clocks:
425           items:
426             - description: bus clock required for AHB bus access
427             - description: bus clock required for downstream bus access and for
428                 the smmu ptw
429             - description: interface clock required to access smmu's registers
430                 through the TCU's programming interface.
431
432   - if:
433       properties:
434         compatible:
435           items:
436             - enum:
437                 - qcom,sm6115-smmu-500
438                 - qcom,sm6125-smmu-500
439             - const: qcom,adreno-smmu
440             - const: qcom,smmu-500
441             - const: arm,mmu-500
442     then:
443       properties:
444         clock-names:
445           items:
446             - const: mem
447             - const: hlos
448             - const: iface
449
450         clocks:
451           items:
452             - description: GPU memory bus clock
453             - description: Voter clock required for HLOS SMMU access
454             - description: Interface clock required for register access
455
456   # Disallow clocks for all other platforms with specific compatibles
457   - if:
458       properties:
459         compatible:
460           contains:
461             enum:
462               - cavium,smmu-v2
463               - marvell,ap806-smmu-500
464               - nvidia,smmu-500
465               - qcom,qcm2290-smmu-500
466               - qcom,qdu1000-smmu-500
467               - qcom,sc7180-smmu-500
468               - qcom,sc8180x-smmu-500
469               - qcom,sdm670-smmu-500
470               - qcom,sdm845-smmu-500
471               - qcom,sdx55-smmu-500
472               - qcom,sdx65-smmu-500
473               - qcom,sm6350-smmu-500
474               - qcom,sm6375-smmu-500
475               - qcom,sm8350-smmu-500
476               - qcom,sm8450-smmu-500
477               - qcom,sm8550-smmu-500
478     then:
479       properties:
480         clock-names: false
481         clocks: false
482
483   - if:
484       properties:
485         compatible:
486           contains:
487             const: qcom,sm6375-smmu-500
488     then:
489       properties:
490         power-domains:
491           items:
492             - description: SNoC MMU TBU RT GDSC
493             - description: SNoC MMU TBU NRT GDSC
494             - description: SNoC TURING MMU TBU0 GDSC
495
496       required:
497         - power-domains
498     else:
499       properties:
500         power-domains:
501           maxItems: 1
502
503 examples:
504   - |+
505     /* SMMU with stream matching or stream indexing */
506     smmu1: iommu@ba5e0000 {
507             compatible = "arm,smmu-v1";
508             reg = <0xba5e0000 0x10000>;
509             #global-interrupts = <2>;
510             interrupts = <0 32 4>,
511                          <0 33 4>,
512                          <0 34 4>, /* This is the first context interrupt */
513                          <0 35 4>,
514                          <0 36 4>,
515                          <0 37 4>;
516             #iommu-cells = <1>;
517     };
518
519     /* device with two stream IDs, 0 and 7 */
520     master1 {
521             iommus = <&smmu1 0>,
522                      <&smmu1 7>;
523     };
524
525
526     /* SMMU with stream matching */
527     smmu2: iommu@ba5f0000 {
528             compatible = "arm,smmu-v1";
529             reg = <0xba5f0000 0x10000>;
530             #global-interrupts = <2>;
531             interrupts = <0 38 4>,
532                          <0 39 4>,
533                          <0 40 4>, /* This is the first context interrupt */
534                          <0 41 4>,
535                          <0 42 4>,
536                          <0 43 4>;
537             #iommu-cells = <2>;
538     };
539
540     /* device with stream IDs 0 and 7 */
541     master2 {
542             iommus = <&smmu2 0 0>,
543                      <&smmu2 7 0>;
544     };
545
546     /* device with stream IDs 1, 17, 33 and 49 */
547     master3 {
548             iommus = <&smmu2 1 0x30>;
549     };
550
551
552     /* ARM MMU-500 with 10-bit stream ID input configuration */
553     smmu3: iommu@ba600000 {
554             compatible = "arm,mmu-500", "arm,smmu-v2";
555             reg = <0xba600000 0x10000>;
556             #global-interrupts = <2>;
557             interrupts = <0 44 4>,
558                          <0 45 4>,
559                          <0 46 4>, /* This is the first context interrupt */
560                          <0 47 4>,
561                          <0 48 4>,
562                          <0 49 4>;
563             #iommu-cells = <1>;
564             /* always ignore appended 5-bit TBU number */
565             stream-match-mask = <0x7c00>;
566     };
567
568     bus {
569             /* bus whose child devices emit one unique 10-bit stream
570                ID each, but may master through multiple SMMU TBUs */
571             iommu-map = <0 &smmu3 0 0x400>;
572
573
574     };
575
576   - |+
577     /* Qcom's arm,smmu-v2 implementation */
578     #include <dt-bindings/interrupt-controller/arm-gic.h>
579     #include <dt-bindings/interrupt-controller/irq.h>
580     smmu4: iommu@d00000 {
581       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
582       reg = <0xd00000 0x10000>;
583
584       #global-interrupts = <1>;
585       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
586              <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
587              <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
588       #iommu-cells = <1>;
589       power-domains = <&mmcc 0>;
590
591       clocks = <&mmcc 123>,
592         <&mmcc 124>;
593       clock-names = "bus", "iface";
594     };