Documentation/devicetree/bindings/iommu/arm,smmu.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM System MMU Architecture Implementation
   8
   9 maintainers:
  10   - Will Deacon <will@kernel.org>
  11   - Robin Murphy <Robin.Murphy@arm.com>
  12
  13 description: |+
  14   ARM SoCs may contain an implementation of the ARM System Memory
  15   Management Unit Architecture, which can be used to provide 1 or 2 stages
  16   of address translation to bus masters external to the CPU.
  17
  18   The SMMU may also raise interrupts in response to various fault
  19   conditions.
  20
  21 properties:
  22   $nodename:
  23     pattern: "^iommu@[0-9a-f]*"
  24   compatible:
  25     oneOf:
  26       - description: Qcom SoCs implementing "arm,smmu-v2"
  27         items:
  28           - enum:
  29               - qcom,msm8996-smmu-v2
  30               - qcom,msm8998-smmu-v2
  31               - qcom,sdm630-smmu-v2
  32               - qcom,sm6375-smmu-v2
  33           - const: qcom,smmu-v2
  34
  35       - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
  36         items:
  37           - enum:
  38               - qcom,qcm2290-smmu-500
  39               - qcom,qdu1000-smmu-500
  40               - qcom,sa8775p-smmu-500
  41               - qcom,sc7180-smmu-500
  42               - qcom,sc7280-smmu-500
  43               - qcom,sc8180x-smmu-500
  44               - qcom,sc8280xp-smmu-500
  45               - qcom,sdm670-smmu-500
  46               - qcom,sdm845-smmu-500
  47               - qcom,sdx55-smmu-500
  48               - qcom,sdx65-smmu-500
  49               - qcom,sdx75-smmu-500
  50               - qcom,sm6115-smmu-500
  51               - qcom,sm6125-smmu-500
  52               - qcom,sm6350-smmu-500
  53               - qcom,sm6375-smmu-500
  54               - qcom,sm8150-smmu-500
  55               - qcom,sm8250-smmu-500
  56               - qcom,sm8350-smmu-500
  57               - qcom,sm8450-smmu-500
  58               - qcom,sm8550-smmu-500
  59               - qcom,sm8650-smmu-500
  60               - qcom,x1e80100-smmu-500
  61           - const: qcom,smmu-500
  62           - const: arm,mmu-500
  63
  64       - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
  65         deprecated: true
  66         items:
  67           # Do not add additional SoC to this list. Instead use two previous lists.
  68           - enum:
  69               - qcom,qcm2290-smmu-500
  70               - qcom,sc7180-smmu-500
  71               - qcom,sc7280-smmu-500
  72               - qcom,sc8180x-smmu-500
  73               - qcom,sc8280xp-smmu-500
  74               - qcom,sdm845-smmu-500
  75               - qcom,sm6115-smmu-500
  76               - qcom,sm6350-smmu-500
  77               - qcom,sm6375-smmu-500
  78               - qcom,sm8150-smmu-500
  79               - qcom,sm8250-smmu-500
  80               - qcom,sm8350-smmu-500
  81               - qcom,sm8450-smmu-500
  82           - const: arm,mmu-500
  83       - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
  84         items:
  85           - enum:
  86               - qcom,sa8775p-smmu-500
  87               - qcom,sc7280-smmu-500
  88               - qcom,sc8280xp-smmu-500
  89               - qcom,sm6115-smmu-500
  90               - qcom,sm6125-smmu-500
  91               - qcom,sm8150-smmu-500
  92               - qcom,sm8250-smmu-500
  93               - qcom,sm8350-smmu-500
  94               - qcom,sm8450-smmu-500
  95               - qcom,sm8550-smmu-500
  96           - const: qcom,adreno-smmu
  97           - const: qcom,smmu-500
  98           - const: arm,mmu-500
  99       - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
 100         deprecated: true
 101         items:
 102           # Do not add additional SoC to this list. Instead use previous list.
 103           - enum:
 104               - qcom,sc7280-smmu-500
 105               - qcom,sm8150-smmu-500
 106               - qcom,sm8250-smmu-500
 107           - const: qcom,adreno-smmu
 108           - const: arm,mmu-500
 109       - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
 110         items:
 111           - enum:
 112               - qcom,msm8996-smmu-v2
 113               - qcom,sc7180-smmu-v2
 114               - qcom,sdm630-smmu-v2
 115               - qcom,sdm845-smmu-v2
 116               - qcom,sm6350-smmu-v2
 117               - qcom,sm7150-smmu-v2
 118           - const: qcom,adreno-smmu
 119           - const: qcom,smmu-v2
 120       - description: Qcom Adreno GPUs on Google Cheza platform
 121         items:
 122           - const: qcom,sdm845-smmu-v2
 123           - const: qcom,smmu-v2
 124       - description: Marvell SoCs implementing "arm,mmu-500"
 125         items:
 126           - const: marvell,ap806-smmu-500
 127           - const: arm,mmu-500
 128       - description: NVIDIA SoCs that require memory controller interaction
 129           and may program multiple ARM MMU-500s identically with the memory
 130           controller interleaving translations between multiple instances
 131           for improved performance.
 132         items:
 133           - enum:
 134               - nvidia,tegra186-smmu
 135               - nvidia,tegra194-smmu
 136               - nvidia,tegra234-smmu
 137           - const: nvidia,smmu-500
 138       - items:
 139           - const: arm,mmu-500
 140           - const: arm,smmu-v2
 141       - items:
 142           - enum:
 143               - arm,mmu-400
 144               - arm,mmu-401
 145           - const: arm,smmu-v1
 146       - enum:
 147           - arm,smmu-v1
 148           - arm,smmu-v2
 149           - arm,mmu-400
 150           - arm,mmu-401
 151           - arm,mmu-500
 152           - cavium,smmu-v2
 153
 154   reg:
 155     minItems: 1
 156     maxItems: 2
 157
 158   '#global-interrupts':
 159     description: The number of global interrupts exposed by the device.
 160     $ref: /schemas/types.yaml#/definitions/uint32
 161     minimum: 0
 162     maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
 163
 164   '#iommu-cells':
 165     enum: [ 1, 2 ]
 166     description: |
 167       See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
 168       value of 1, each IOMMU specifier represents a distinct stream ID emitted
 169       by that device into the relevant SMMU.
 170
 171       SMMUs with stream matching support and complex masters may use a value of
 172       2, where the second cell of the IOMMU specifier represents an SMR mask to
 173       combine with the ID in the first cell.  Care must be taken to ensure the
 174       set of matched IDs does not result in conflicts.
 175
 176   interrupts:
 177     minItems: 1
 178     maxItems: 388   # 260 plus 128 contexts
 179     description: |
 180       Interrupt list, with the first #global-interrupts entries corresponding to
 181       the global interrupts and any following entries corresponding to context
 182       interrupts, specified in order of their indexing by the SMMU.
 183
 184       For SMMUv2 implementations, there must be exactly one interrupt per
 185       context bank. In the case of a single, combined interrupt, it must be
 186       listed multiple times.
 187
 188   dma-coherent:
 189     description: |
 190       Present if page table walks made by the SMMU are cache coherent with the
 191       CPU.
 192
 193       NOTE: this only applies to the SMMU itself, not masters connected
 194       upstream of the SMMU.
 195
 196   calxeda,smmu-secure-config-access:
 197     type: boolean
 198     description:
 199       Enable proper handling of buggy implementations that always use secure
 200       access to SMMU configuration registers. In this case non-secure aliases of
 201       secure registers have to be used during SMMU configuration.
 202
 203   stream-match-mask:
 204     $ref: /schemas/types.yaml#/definitions/uint32
 205     description: |
 206       For SMMUs supporting stream matching and using #iommu-cells = <1>,
 207       specifies a mask of bits to ignore when matching stream IDs (e.g. this may
 208       be programmed into the SMRn.MASK field of every stream match register
 209       used). For cases where it is desirable to ignore some portion of every
 210       Stream ID (e.g. for certain MMU-500 configurations given globally unique
 211       input IDs). This property is not valid for SMMUs using stream indexing, or
 212       using stream matching with #iommu-cells = <2>, and may be ignored if
 213       present in such cases.
 214
 215   clock-names:
 216     minItems: 1
 217     maxItems: 7
 218
 219   clocks:
 220     minItems: 1
 221     maxItems: 7
 222
 223   power-domains:
 224     minItems: 1
 225     maxItems: 3
 226
 227   nvidia,memory-controller:
 228     description: |
 229       A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
 230       The memory controller needs to be programmed with a mapping of memory
 231       client IDs to ARM SMMU stream IDs.
 232
 233       If this property is absent, the mapping programmed by early firmware
 234       will be used and it is not guaranteed that IOMMU translations will be
 235       enabled for any given device.
 236     $ref: /schemas/types.yaml#/definitions/phandle
 237
 238 required:
 239   - compatible
 240   - reg
 241   - '#global-interrupts'
 242   - '#iommu-cells'
 243   - interrupts
 244
 245 additionalProperties: false
 246
 247 allOf:
 248   - if:
 249       properties:
 250         compatible:
 251           contains:
 252             enum:
 253               - nvidia,tegra186-smmu
 254               - nvidia,tegra194-smmu
 255               - nvidia,tegra234-smmu
 256     then:
 257       properties:
 258         reg:
 259           minItems: 1
 260           maxItems: 2
 261
 262       # The reference to the memory controller is required to ensure that the
 263       # memory client to stream ID mapping can be done synchronously with the
 264       # IOMMU attachment.
 265       required:
 266         - nvidia,memory-controller
 267     else:
 268       properties:
 269         reg:
 270           maxItems: 1
 271
 272   - if:
 273       properties:
 274         compatible:
 275           contains:
 276             enum:
 277               - qcom,msm8998-smmu-v2
 278               - qcom,sdm630-smmu-v2
 279     then:
 280       anyOf:
 281         - properties:
 282             clock-names:
 283               items:
 284                 - const: bus
 285             clocks:
 286               items:
 287                 - description: bus clock required for downstream bus access and for
 288                     the smmu ptw
 289         - properties:
 290             clock-names:
 291               items:
 292                 - const: iface
 293                 - const: mem
 294                 - const: mem_iface
 295             clocks:
 296               items:
 297                 - description: interface clock required to access smmu's registers
 298                     through the TCU's programming interface.
 299                 - description: bus clock required for memory access
 300                 - description: bus clock required for GPU memory access
 301         - properties:
 302             clock-names:
 303               items:
 304                 - const: iface-mm
 305                 - const: iface-smmu
 306                 - const: bus-smmu
 307             clocks:
 308               items:
 309                 - description: interface clock required to access mnoc's registers
 310                     through the TCU's programming interface.
 311                 - description: interface clock required to access smmu's registers
 312                     through the TCU's programming interface.
 313                 - description: bus clock required for the smmu ptw
 314
 315   - if:
 316       properties:
 317         compatible:
 318           contains:
 319             enum:
 320               - qcom,sm6375-smmu-v2
 321     then:
 322       anyOf:
 323         - properties:
 324             clock-names:
 325               items:
 326                 - const: bus
 327             clocks:
 328               items:
 329                 - description: bus clock required for downstream bus access and for
 330                     the smmu ptw
 331         - properties:
 332             clock-names:
 333               items:
 334                 - const: iface
 335                 - const: mem
 336                 - const: mem_iface
 337             clocks:
 338               items:
 339                 - description: interface clock required to access smmu's registers
 340                     through the TCU's programming interface.
 341                 - description: bus clock required for memory access
 342                 - description: bus clock required for GPU memory access
 343         - properties:
 344             clock-names:
 345               items:
 346                 - const: iface-mm
 347                 - const: iface-smmu
 348                 - const: bus-mm
 349                 - const: bus-smmu
 350             clocks:
 351               items:
 352                 - description: interface clock required to access mnoc's registers
 353                     through the TCU's programming interface.
 354                 - description: interface clock required to access smmu's registers
 355                     through the TCU's programming interface.
 356                 - description: bus clock required for downstream bus access
 357                 - description: bus clock required for the smmu ptw
 358
 359   - if:
 360       properties:
 361         compatible:
 362           contains:
 363             enum:
 364               - qcom,msm8996-smmu-v2
 365               - qcom,sc7180-smmu-v2
 366               - qcom,sdm845-smmu-v2
 367     then:
 368       properties:
 369         clock-names:
 370           items:
 371             - const: bus
 372             - const: iface
 373
 374         clocks:
 375           items:
 376             - description: bus clock required for downstream bus access and for
 377                 the smmu ptw
 378             - description: interface clock required to access smmu's registers
 379                 through the TCU's programming interface.
 380
 381   - if:
 382       properties:
 383         compatible:
 384           contains:
 385             enum:
 386               - qcom,sa8775p-smmu-500
 387               - qcom,sc7280-smmu-500
 388               - qcom,sc8280xp-smmu-500
 389     then:
 390       properties:
 391         clock-names:
 392           items:
 393             - const: gcc_gpu_memnoc_gfx_clk
 394             - const: gcc_gpu_snoc_dvm_gfx_clk
 395             - const: gpu_cc_ahb_clk
 396             - const: gpu_cc_hlos1_vote_gpu_smmu_clk
 397             - const: gpu_cc_cx_gmu_clk
 398             - const: gpu_cc_hub_cx_int_clk
 399             - const: gpu_cc_hub_aon_clk
 400
 401         clocks:
 402           items:
 403             - description: GPU memnoc_gfx clock
 404             - description: GPU snoc_dvm_gfx clock
 405             - description: GPU ahb clock
 406             - description: GPU hlos1_vote_GPU smmu clock
 407             - description: GPU cx_gmu clock
 408             - description: GPU hub_cx_int clock
 409             - description: GPU hub_aon clock
 410
 411   - if:
 412       properties:
 413         compatible:
 414           contains:
 415             enum:
 416               - qcom,sm6350-smmu-v2
 417               - qcom,sm7150-smmu-v2
 418               - qcom,sm8150-smmu-500
 419               - qcom,sm8250-smmu-500
 420     then:
 421       properties:
 422         clock-names:
 423           items:
 424             - const: ahb
 425             - const: bus
 426             - const: iface
 427
 428         clocks:
 429           items:
 430             - description: bus clock required for AHB bus access
 431             - description: bus clock required for downstream bus access and for
 432                 the smmu ptw
 433             - description: interface clock required to access smmu's registers
 434                 through the TCU's programming interface.
 435
 436   - if:
 437       properties:
 438         compatible:
 439           items:
 440             - enum:
 441                 - qcom,sm8350-smmu-500
 442             - const: qcom,adreno-smmu
 443             - const: qcom,smmu-500
 444             - const: arm,mmu-500
 445     then:
 446       properties:
 447         clock-names:
 448           items:
 449             - const: bus
 450             - const: iface
 451             - const: ahb
 452             - const: hlos1_vote_gpu_smmu
 453             - const: cx_gmu
 454             - const: hub_cx_int
 455             - const: hub_aon
 456         clocks:
 457           minItems: 7
 458           maxItems: 7
 459
 460   - if:
 461       properties:
 462         compatible:
 463           items:
 464             - enum:
 465                 - qcom,sm6115-smmu-500
 466                 - qcom,sm6125-smmu-500
 467             - const: qcom,adreno-smmu
 468             - const: qcom,smmu-500
 469             - const: arm,mmu-500
 470     then:
 471       properties:
 472         clock-names:
 473           items:
 474             - const: mem
 475             - const: hlos
 476             - const: iface
 477
 478         clocks:
 479           items:
 480             - description: GPU memory bus clock
 481             - description: Voter clock required for HLOS SMMU access
 482             - description: Interface clock required for register access
 483
 484   - if:
 485       properties:
 486         compatible:
 487           items:
 488             - const: qcom,sm8450-smmu-500
 489             - const: qcom,adreno-smmu
 490             - const: qcom,smmu-500
 491             - const: arm,mmu-500
 492
 493     then:
 494       properties:
 495         clock-names:
 496           items:
 497             - const: gmu
 498             - const: hub
 499             - const: hlos
 500             - const: bus
 501             - const: iface
 502             - const: ahb
 503
 504         clocks:
 505           items:
 506             - description: GMU clock
 507             - description: GPU HUB clock
 508             - description: HLOS vote clock
 509             - description: GPU memory bus clock
 510             - description: GPU SNoC bus clock
 511             - description: GPU AHB clock
 512
 513   - if:
 514       properties:
 515         compatible:
 516           items:
 517             - const: qcom,sm8550-smmu-500
 518             - const: qcom,adreno-smmu
 519             - const: qcom,smmu-500
 520             - const: arm,mmu-500
 521     then:
 522       properties:
 523         clock-names:
 524           items:
 525             - const: hlos
 526             - const: bus
 527             - const: iface
 528             - const: ahb
 529
 530         clocks:
 531           items:
 532             - description: HLOS vote clock
 533             - description: GPU memory bus clock
 534             - description: GPU SNoC bus clock
 535             - description: GPU AHB clock
 536
 537   # Disallow clocks for all other platforms with specific compatibles
 538   - if:
 539       properties:
 540         compatible:
 541           contains:
 542             enum:
 543               - cavium,smmu-v2
 544               - marvell,ap806-smmu-500
 545               - nvidia,smmu-500
 546               - qcom,qcm2290-smmu-500
 547               - qcom,qdu1000-smmu-500
 548               - qcom,sc7180-smmu-500
 549               - qcom,sc8180x-smmu-500
 550               - qcom,sdm670-smmu-500
 551               - qcom,sdm845-smmu-500
 552               - qcom,sdx55-smmu-500
 553               - qcom,sdx65-smmu-500
 554               - qcom,sm6350-smmu-500
 555               - qcom,sm6375-smmu-500
 556               - qcom,sm8650-smmu-500
 557               - qcom,x1e80100-smmu-500
 558     then:
 559       properties:
 560         clock-names: false
 561         clocks: false
 562
 563   - if:
 564       properties:
 565         compatible:
 566           contains:
 567             const: qcom,sm6375-smmu-500
 568     then:
 569       properties:
 570         power-domains:
 571           items:
 572             - description: SNoC MMU TBU RT GDSC
 573             - description: SNoC MMU TBU NRT GDSC
 574             - description: SNoC TURING MMU TBU0 GDSC
 575
 576       required:
 577         - power-domains
 578     else:
 579       properties:
 580         power-domains:
 581           maxItems: 1
 582
 583 examples:
 584   - |+
 585     /* SMMU with stream matching or stream indexing */
 586     smmu1: iommu@ba5e0000 {
 587             compatible = "arm,smmu-v1";
 588             reg = <0xba5e0000 0x10000>;
 589             #global-interrupts = <2>;
 590             interrupts = <0 32 4>,
 591                          <0 33 4>,
 592                          <0 34 4>, /* This is the first context interrupt */
 593                          <0 35 4>,
 594                          <0 36 4>,
 595                          <0 37 4>;
 596             #iommu-cells = <1>;
 597     };
 598
 599     /* device with two stream IDs, 0 and 7 */
 600     master1 {
 601             iommus = <&smmu1 0>,
 602                      <&smmu1 7>;
 603     };
 604
 605
 606     /* SMMU with stream matching */
 607     smmu2: iommu@ba5f0000 {
 608             compatible = "arm,smmu-v1";
 609             reg = <0xba5f0000 0x10000>;
 610             #global-interrupts = <2>;
 611             interrupts = <0 38 4>,
 612                          <0 39 4>,
 613                          <0 40 4>, /* This is the first context interrupt */
 614                          <0 41 4>,
 615                          <0 42 4>,
 616                          <0 43 4>;
 617             #iommu-cells = <2>;
 618     };
 619
 620     /* device with stream IDs 0 and 7 */
 621     master2 {
 622             iommus = <&smmu2 0 0>,
 623                      <&smmu2 7 0>;
 624     };
 625
 626     /* device with stream IDs 1, 17, 33 and 49 */
 627     master3 {
 628             iommus = <&smmu2 1 0x30>;
 629     };
 630
 631
 632     /* ARM MMU-500 with 10-bit stream ID input configuration */
 633     smmu3: iommu@ba600000 {
 634             compatible = "arm,mmu-500", "arm,smmu-v2";
 635             reg = <0xba600000 0x10000>;
 636             #global-interrupts = <2>;
 637             interrupts = <0 44 4>,
 638                          <0 45 4>,
 639                          <0 46 4>, /* This is the first context interrupt */
 640                          <0 47 4>,
 641                          <0 48 4>,
 642                          <0 49 4>;
 643             #iommu-cells = <1>;
 644             /* always ignore appended 5-bit TBU number */
 645             stream-match-mask = <0x7c00>;
 646     };
 647
 648     bus {
 649             /* bus whose child devices emit one unique 10-bit stream
 650                ID each, but may master through multiple SMMU TBUs */
 651             iommu-map = <0 &smmu3 0 0x400>;
 652
 653
 654     };
 655
 656   - |+
 657     /* Qcom's arm,smmu-v2 implementation */
 658     #include <dt-bindings/interrupt-controller/arm-gic.h>
 659     #include <dt-bindings/interrupt-controller/irq.h>
 660     smmu4: iommu@d00000 {
 661       compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 662       reg = <0xd00000 0x10000>;
 663
 664       #global-interrupts = <1>;
 665       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 666              <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 667              <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
 668       #iommu-cells = <1>;
 669       power-domains = <&mmcc 0>;
 670
 671       clocks = <&mmcc 123>,
 672         <&mmcc 124>;
 673       clock-names = "bus", "iface";
 674     };