1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations for
4 dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
8 - compatible: "snps,archs-idu-intc"
9 - interrupt-controller: This is an interrupt controller.
10 - #interrupt-cells: Must be <1>.
12 Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
13 of the particular interrupt line of IDU corresponds to the line N+24 of the
14 core interrupt controller.
16 intc accessed via the special ARC AUX register interface, hence "reg" property
20 core_intc: core-interrupt-controller {
21 compatible = "snps,archs-intc";
23 #interrupt-cells = <1>;
26 idu_intc: idu-interrupt-controller {
27 compatible = "snps,archs-idu-intc";
29 interrupt-parent = <&core_intc>;
30 #interrupt-cells = <1>;
33 some_device: serial@c0fc1000 {
34 interrupt-parent = <&idu_intc>;
35 interrupts = <0>; /* upstream idu IRQ #24 */