1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PDC interrupt controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14 Power Domain Controller (PDC) that is on always-on domain. In addition to
15 providing power control for the power domains, the hardware also has an
16 interrupt controller that can be used to help detect edge low interrupts as
17 well detect interrupts when the GIC is non-operational.
19 GIC is parent interrupt controller at the highest level. Platform interrupt
20 controller PDC is next in hierarchy, followed by others. Drivers requiring
21 wakeup capabilities of their device interrupts routed through the PDC, must
22 specify PDC as their interrupt controller and request the PDC port associated
23 with the GIC interrupt. See example below.
49 - description: PDC base register region
50 - description: Edge or Level config register for SPI interrupts
55 interrupt-controller: true
58 $ref: /schemas/types.yaml#/definitions/uint32-matrix
60 maxItems: 128 # no hard limit
63 - description: starting PDC port
64 - description: GIC hwirq number for the PDC port
65 - description: number of interrupts in sequence
67 Specifies the PDC pin offset and the number of PDC ports.
68 The tuples indicates the valid mapping of valid PDC ports
69 and their hwirq mapping.
75 - interrupt-controller
78 additionalProperties: false
82 #include <dt-bindings/interrupt-controller/irq.h>
84 pdc: interrupt-controller@b220000 {
85 compatible = "qcom,sdm845-pdc", "qcom,pdc";
86 reg = <0xb220000 0x30000>;
87 qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
88 #interrupt-cells = <2>;
89 interrupt-parent = <&intc>;
94 interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;