Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: PDC interrupt controller
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description: |
  13   Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
  14   Power Domain Controller (PDC) that is on always-on domain. In addition to
  15   providing power control for the power domains, the hardware also has an
  16   interrupt controller that can be used to help detect edge low interrupts as
  17   well detect interrupts when the GIC is non-operational.
  18
  19   GIC is parent interrupt controller at the highest level. Platform interrupt
  20   controller PDC is next in hierarchy, followed by others. Drivers requiring
  21   wakeup capabilities of their device interrupts routed through the PDC, must
  22   specify PDC as their interrupt controller and request the PDC port associated
  23   with the GIC interrupt. See example below.
  24
  25 properties:
  26   compatible:
  27     items:
  28       - enum:
  29           - qcom,qdu1000-pdc
  30           - qcom,sa8775p-pdc
  31           - qcom,sc7180-pdc
  32           - qcom,sc7280-pdc
  33           - qcom,sc8280xp-pdc
  34           - qcom,sdm670-pdc
  35           - qcom,sdm845-pdc
  36           - qcom,sdx55-pdc
  37           - qcom,sdx65-pdc
  38           - qcom,sdx75-pdc
  39           - qcom,sm4450-pdc
  40           - qcom,sm6350-pdc
  41           - qcom,sm8150-pdc
  42           - qcom,sm8250-pdc
  43           - qcom,sm8350-pdc
  44           - qcom,sm8450-pdc
  45           - qcom,sm8550-pdc
  46           - qcom,sm8650-pdc
  47           - qcom,x1e80100-pdc
  48       - const: qcom,pdc
  49
  50   reg:
  51     minItems: 1
  52     items:
  53       - description: PDC base register region
  54       - description: Edge or Level config register for SPI interrupts
  55
  56   '#interrupt-cells':
  57     const: 2
  58
  59   interrupt-controller: true
  60
  61   qcom,pdc-ranges:
  62     $ref: /schemas/types.yaml#/definitions/uint32-matrix
  63     minItems: 1
  64     maxItems: 128 # no hard limit
  65     items:
  66       items:
  67         - description: starting PDC port
  68         - description: GIC hwirq number for the PDC port
  69         - description: number of interrupts in sequence
  70     description: |
  71       Specifies the PDC pin offset and the number of PDC ports.
  72       The tuples indicates the valid mapping of valid PDC ports
  73       and their hwirq mapping.
  74
  75 required:
  76   - compatible
  77   - reg
  78   - '#interrupt-cells'
  79   - interrupt-controller
  80   - qcom,pdc-ranges
  81
  82 additionalProperties: false
  83
  84 examples:
  85   - |
  86     #include <dt-bindings/interrupt-controller/irq.h>
  87
  88     pdc: interrupt-controller@b220000 {
  89         compatible = "qcom,sdm845-pdc", "qcom,pdc";
  90         reg = <0xb220000 0x30000>;
  91         qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
  92         #interrupt-cells = <2>;
  93         interrupt-parent = <&intc>;
  94         interrupt-controller;
  95     };
  96
  97     wake-device {
  98         interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
  99     };