1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcom MPM Interrupt Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
14 MSM Power Manager (MPM) that is in always-on domain. In addition to managing
15 resources during sleep, the hardware also has an interrupt controller that
16 monitors the interrupts when the system is asleep, wakes up the APSS when
17 one of these interrupts occur and replays it to GIC interrupt controller
18 after GIC becomes operational.
21 - $ref: /schemas/interrupt-controller.yaml#
31 Specifies the base address and size of vMPM registers in RPM MSG RAM.
36 Specify the IRQ used by RPM to wakeup APSS.
41 Specify the mailbox used to notify RPM for writing vMPM registers.
43 interrupt-controller: true
48 The first cell is the MPM pin number for the interrupt, and the second
53 Specify the total MPM pin count that a SoC supports.
54 $ref: /schemas/types.yaml#/definitions/uint32
58 A set of MPM pin numbers and the corresponding GIC SPIs.
59 $ref: /schemas/types.yaml#/definitions/uint32-matrix
62 - description: MPM pin number
63 - description: GIC SPI number for the MPM pin
70 - interrupt-controller
75 additionalProperties: false
79 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 mpm: interrupt-controller@45f01b8 {
81 compatible = "qcom,mpm";
82 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
83 reg = <0x45f01b8 0x1000>;
84 mboxes = <&apcs_glb 1>;
86 #interrupt-cells = <2>;
87 interrupt-parent = <&intc>;
88 qcom,mpm-pin-count = <96>;
89 qcom,mpm-pin-map = <2 275>,