1 This document describes the generic device tree binding for MSI controllers and
4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
5 write to an MMIO address.
7 MSIs were originally specified by PCI (and are used with PCIe), but may also be
8 used with other busses, and hence a mechanism is required to relate devices on
9 those busses to the MSI controllers which they are capable of using,
10 potentially including additional information.
12 MSIs are distinguished by some combination of:
14 - The doorbell (the MMIO address written to).
16 Devices may be configured by software to write to arbitrary doorbells which
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
21 Devices may be configured to write an arbitrary payload chosen by software.
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
26 Typically this is neither configurable nor probeable, and depends on the path
27 taken through the memory system (i.e. it is a property of the combination of
28 MSI controller and device rather than a property of either in isolation).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
47 Typically this will encode information related to sideband data, and will
48 not encode doorbells or payloads as these can be configured dynamically.
50 The meaning of the msi-specifier is defined by the device tree binding of
51 the specific MSI controller.
57 MSI clients are devices which generate MSIs. For each MSI they wish to
58 generate, the doorbell and payload may be configured, though sideband
59 information may not be configurable.
64 - msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
65 controller which the device is capable of using.
67 This property is unordered, and MSIs may be allocated from any combination of
68 MSI controllers listed in the msi-parent property.
70 If a device has restrictions on the allocation of MSIs, these restrictions
71 must be described with additional properties.
73 When #msi-cells is non-zero, busses with an msi-parent will require
74 additional properties to describe the relationship between devices on the bus
75 and the set of MSIs they can potentially generate.
85 msi_a: msi-controller@a {
87 compatible = "vendor-a,some-controller";
89 /* No sideband data, so #msi-cells omitted */
92 msi_b: msi-controller@b {
94 compatible = "vendor-b,another-controller";
96 /* Each device has some unique ID */
100 msi_c: msi-controller@c {
102 compatible = "vendor-b,another-controller";
104 /* Each device has some unique ID */
110 compatible = "vendor-c,some-device";
112 /* Can only generate MSIs to msi_a */
113 msi-parent = <&msi_a>;
118 compatible = "vendor-c,some-device";
121 * Can generate MSIs to either A or B.
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
128 compatible = "vendor-c,some-device";
130 * Has different IDs at each MSI controller.
131 * Can generate MSIs to all of the MSI controllers.
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;