1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <Frank.Li@nxp.com>
13 The Messaging Unit module enables two processors within the SoC to
14 communicate and coordinate by passing messages (e.g. data, status
15 and control) through the MU interface. The MU also provides the ability
16 for one processor (A side) to signal the other processor (B side) using
19 Because the MU manages the messaging between processors, the MU uses
20 different clocks (from each side of the different peripheral buses).
21 Therefore, the MU must synchronize the accesses from one side to the
22 other. The MU accomplishes synchronization using two sets of matching
23 registers (Processor A-side, Processor B-side).
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
36 - fsl,imx8ulp-mu-msi-s4
40 - description: a side register base address
41 - description: b side register base address
45 - const: processor-a-side
46 - const: processor-b-side
49 description: a side interrupt number.
57 - description: a side power domain
58 - description: b side power domain
62 - const: processor-a-side
63 - const: processor-b-side
65 interrupt-controller: true
76 - interrupt-controller
80 additionalProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/firmware/imx/rsrc.h>
87 msi-controller@5d270000 {
88 compatible = "fsl,imx6sx-mu-msi";
92 reg = <0x5d270000 0x10000>, /* A side */
93 <0x5d300000 0x10000>; /* B side */
94 reg-names = "processor-a-side", "processor-b-side";
95 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
96 power-domains = <&pd IMX_SC_R_MU_12A>,
97 <&pd IMX_SC_R_MU_12B>;
98 power-domain-names = "processor-a-side", "processor-b-side";