1 * ARM Generic Interrupt Controller, version 3
3 AArch64 SMP cores are often associated with a GICv3, providing Private
4 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
8 Main node required properties:
10 - compatible : should at least contain "arm,gic-v3".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
13 interrupt source. Must be a single cell with a value of at least 3.
14 If the system requires describing PPI affinity, then the value must
17 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
18 interrupts. Other values are reserved for future use.
20 The 2nd cell contains the interrupt number for the interrupt type.
21 SPI interrupts are in the range [0-987]. PPI interrupts are in the
24 The 3rd cell is the flags, encoded as follows:
25 bits[3:0] trigger type and level flags.
29 The 4th cell is a phandle to a node describing a set of CPUs this
30 interrupt is affine to. The interrupt must be a PPI, and the node
31 pointed must be a subnode of the "ppi-partitions" subnode. For
32 interrupt types other than PPI or PPIs that are not partitionned,
33 this cell must be zero. See the "ppi-partitions" node description
36 Cells 5 and beyond are reserved for future use and must have a value
39 - reg : Specifies base physical address(s) and size of the GIC
40 registers, in the following order:
41 - GIC Distributor interface (GICD)
42 - GIC Redistributors (GICR), one range per redistributor region
43 - GIC CPU interface (GICC)
44 - GIC Hypervisor interface (GICH)
45 - GIC Virtual CPU interface (GICV)
47 GICC, GICH and GICV are optional.
49 - interrupts : Interrupt source of the VGIC maintenance interrupt.
53 - redistributor-stride : If using padding pages, specifies the stride
54 of consecutive redistributors. Must be a multiple of 64kB.
56 - #redistributor-regions: The number of independent contiguous regions
57 occupied by the redistributors. Required if more than one such
60 - msi-controller: Boolean property. Identifies the node as an MSI
61 controller. Only present if the Message Based Interrupt
62 functionnality is being exposed by the HW, and the mbi-ranges
65 - mbi-ranges: A list of pairs <intid span>, where "intid" is the first
66 SPI of a range that can be used an MBI, and "span" the size of that
67 range. Multiple ranges can be provided. Requires "msi-controller" to
70 - mbi-alias: Address property. Base address of an alias of the GICD
71 region containing only the {SET,CLR}SPI registers to be used if
72 isolation is required, and if supported by the HW.
76 PPI affinity can be expressed as a single "ppi-partitions" node,
77 containing a set of sub-nodes, each with the following property:
78 - affinity: Should be a list of phandles to CPU nodes (as described in
79 Documentation/devicetree/bindings/arm/cpus.txt).
81 GICv3 has one or more Interrupt Translation Services (ITS) that are
82 used to route Message Signalled Interrupts (MSI) to the CPUs.
84 These nodes must have the following properties:
85 - compatible : Should at least contain "arm,gic-v3-its".
86 - msi-controller : Boolean property. Identifies the node as an MSI controller
87 - #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
88 which will generate the MSI.
89 - reg: Specifies the base physical address and size of the ITS
93 - socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
94 address and size of the pre-ITS window.
96 The main GIC node must contain the appropriate #address-cells,
97 #size-cells and ranges properties for the reg property of all ITS
102 gic: interrupt-controller@2cf00000 {
103 compatible = "arm,gic-v3";
104 #interrupt-cells = <3>;
105 #address-cells = <2>;
108 interrupt-controller;
109 reg = <0x0 0x2f000000 0 0x10000>, // GICD
110 <0x0 0x2f100000 0 0x200000>, // GICR
111 <0x0 0x2c000000 0 0x2000>, // GICC
112 <0x0 0x2c010000 0 0x2000>, // GICH
113 <0x0 0x2c020000 0 0x2000>; // GICV
114 interrupts = <1 9 4>;
117 mbi-ranges = <256 128>;
120 compatible = "arm,gic-v3-its";
123 reg = <0x0 0x2c200000 0 0x20000>;
127 gic: interrupt-controller@2c010000 {
128 compatible = "arm,gic-v3";
129 #interrupt-cells = <4>;
130 #address-cells = <2>;
133 interrupt-controller;
134 redistributor-stride = <0x0 0x40000>; // 256kB stride
135 #redistributor-regions = <2>;
136 reg = <0x0 0x2c010000 0 0x10000>, // GICD
137 <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
138 <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
139 <0x0 0x2c040000 0 0x2000>, // GICC
140 <0x0 0x2c060000 0 0x2000>, // GICH
141 <0x0 0x2c080000 0 0x2000>; // GICV
142 interrupts = <1 9 4>;
145 compatible = "arm,gic-v3-its";
148 reg = <0x0 0x2c200000 0 0x20000>;
152 compatible = "arm,gic-v3-its";
155 reg = <0x0 0x2c400000 0 0x20000>;
159 part0: interrupt-partition-0 {
160 affinity = <&cpu0 &cpu2>;
163 part1: interrupt-partition-1 {
164 affinity = <&cpu1 &cpu3>;
172 interrupts = <1 1 4 &part0>;