1 Amlogic meson GPIO interrupt controller
3 Meson SoCs contains an interrupt controller which is able to watch the SoC
4 pads and generate an interrupt on edge or level. The controller is essentially
5 a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
6 or level and polarity. It does not expose all 256 mux inputs because the
7 documentation shows that the upper part is not mapped to any pad. The actual
8 number of interrupt exposed depends on the SoC.
12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
18 - reg : Specifies base physical address and size of the registers.
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
21 interrupt source. The value must be 2.
22 - meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
23 are the hwirqs used on the parent interrupt controller.
27 gpio_interrupt: interrupt-controller@9880 {
28 compatible = "amlogic,meson-gxbb-gpio-intc",
29 "amlogic,meson-gpio-intc";
30 reg = <0x0 0x9880 0x0 0x10>;
32 #interrupt-cells = <2>;
33 meson,channel-interrupts = <64 65 66 67 68 69 70 71>;